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參數(shù)資料
| 型號： | XRT73L03A |
| 廠商： | Exar Corporation |
| 英文描述： | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
| 中文描述： | 三通道DS3/E3/STS-1線路接口單元 |
| 文件頁數(shù)： | 51/62頁 |
| 文件大小： | 494K |
| 代理商： | XRT73L03A |
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XRT73L03A
3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.4
49
b. Operating in the Hardware Mode
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, set the LLB_(n) input pin “High"
and the RLB_(n) input pin "Low".
4.2
T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
M
ODE
.
When a given channel is configured to operate in the
Digital Local Loop-Back Mode, the channel ignores
any signals that are input to the RTIP and RRing input
pins. The Transmitting Terminal Equipment transmits
clock and data into the XRT73L03A via the TPData,
TNData and TxClk input pins. This data is processed
through the Transmit Clock Duty Cycle Adjust PLL
and the HDB3/B3ZS Encoder block. At this point, this
data is looped back to the HDB3/B3ZS Decoder
block. After this post-Loop-Back data has been pro-
cessed through the HDB3/B3ZS Decoder block, it
outputs to the Near-End Receiving Terminal Equip-
ment via the RPOS, RNEG and RxClk output pins.
Figure 35 illustrates the path that the data takes when
the chip is configured to operate in the Digital Local
Loop-Back Mode.
Configure a channel to operate in the Digital Local
Loop-Back Mode by employing either one of the fol-
lowing two-steps:
a. Operating in the Host Mode
To configure Channel (n) to operate in the Digital Lo-
cal Loop-Back Mode, write a "1" into both the LLB
and RLB bit-fields within Command Register CR4-(n).
COMMAND REGISTER CR4-(n)
b. Operating in the Hardware Mode.
COMMAND REGISTER CR4-(n)
D4
D3
D2
D1
D0
X
STS-1/DS3_(n)
E3_(n)
LLB_(n) RLB_(n)
X
X
X
1
0
F
IGURE
35. T
HE
D
IGITAL
L
OCAL
L
OOP
-B
ACK
PATH
WITHIN
A
GIVEN
CHANNEL
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV(_n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData(_n)
TNData_(n)
TxClk_(n)
Notes: 1. (n) = 0, 1 or 2 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in
Hardware Mode.
RLOL_(n) EXClk_(n)
Device
Monitor
MTIP_(n)
MRing(_n)
Transmit
Logic
Duty Cycle Adjust
TxLEV_(n)
TxOFF_(n)
DMO_(n)
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Digital Local
Loop-Back Path
D4
D3
D2
D1
D0
X
STS-1/DS3_(n)
E3_(n)
LLB_(n) RLB_(n)
X
X
X
1
1
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| XRT73L03B | 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT73L03AIV | 制造商:Exar Corporation 功能描述: |
| XRT73L03B | 制造商:EXAR 制造商全稱:EXAR 功能描述:3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT |
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| XRT73L03BIV-F | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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