CLOCK AND
參數(shù)資料
型號(hào)： XRT73L02MIVTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 24/46頁(yè)
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 2CH 100TQFP
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 2/2
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 帶卷 (TR)
XRT73L02M
xr
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
28
5.0.2
CLOCK AND DATA RECOVERY:
The Clock and Data Recovery Circuit extracts the embedded clock, from the sliced digital data stream and pro-
vides the retimed data to the B3ZS (HDB3) decoder.
The Clock Recovery PLL can be in one of the following two modes:
TRAINING MODE:
In the absence of input signals at RTIP_n and RRING_n pins, or when the frequency difference between the
recovered line clock signal and the reference clock applied on the E3/DS3/STS1CLK input pins exceed 0.5%, a
Loss of Lock condition is declared by toggling RLOL_n output pin “High” (in Hardware Mode) or setting the
RLOL_n bit to “1” in the control registers. Also, the clock output on the RxClk_n pins are the same as the refer-
ence clock applied on E3/DS3/STS1CLK pins.
DATA/CLOCK RECOVERY MODE:
In the presence of input line signals on the RTIP_n and RRING_n input pins and when the frequency difference
between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on
the RxClk_n out pins is the Recovered Clock signal.
5.0.3
B3ZS/HDB3 DECODER:
The decoder block takes the output from clock and data recovery block and decodes the B3ZS (for DS3 or
STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data
stream.
When the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three (for
B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on the RLCV_n output
pins to indicate line code violation.
NOTE: In Single- Rail (NRZ) mode, the decoder is bypassed.
5.0.4
LOS (Loss of Signal) Detector:
5.0.4.1
DS3/STS-1 LOS Condition:
A Digital Loss of SIgnal (DLOS) condition occurs when a string of 175 ± 75 consecutive zeros occur on the line.
When the DLOS condition occurs, the DLOS_n bit is set to “1” in the status control register. DLOS condition is
cleared when the detected average pulse density is greater than 33% for 175 ± 75 pulses.
Analog Loss of Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the
threshold as shown in the Table 10.The status of the ALOS condition is reflected in the ALOS_n status control
register.
DS3
0 feet
-16 dB
225 feet
- 15dB
450 feet
- 15dB
STS-1
0 feet
- 17 dB
225 feet
- 16 dB
450 feet
- 16 dB
TABLE 9: INTERFERENCE MARGIN TEST RESULTS
MODE
CABLE LENGTH (ATTENUATION)INTERFERENCE TOLERANCE
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