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參數(shù)資料
| 型號： | XRT7300IVTR |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 15/55頁 |
| 文件大小： | 0K |
| 描述： | IC LIU E3/DS3/STS-1 SGL 44TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.2
18
SYSTEM DESCRIPTION
A functional block diagram of the XRT7300 E3/DS3/
STS-1 Transceiver IC (see Figure 1) shows that the
device contains three distinct sections:
The Transmit Section
The Receive Section
The Microprocessor Serial Interface
THE TRANSMIT SECTION
The Transmit Section accepts TTL/CMOS level sig-
nals from the Terminal Equipment in either a Single-
Rail or Dual-Rail format. The Transmit Section then
takes this data and does the following:
Encodes the data into the B3ZS format if the DS3
or SONET STS-1 Modes have been selected or
into the HDB3 format if the E3 Mode has been
selected.
Converts the CMOS level B3ZS or HDB3 encoded
data into pulses with shapes that are compliant with
the various industry standard pulse template
requirements.
Drives these pulses onto the line via the TTIP and
TRING output pins across a 1:1 Transformer.
NOTE: The Transmit Section drives a "1" (or a Mark) on the
line by driving either a positive or negative polarity pulse
across the 1:1 Transformer within a given bit period. The
Transmit Section drives a "0" (or a Space) onto the line by
driving no pulse onto the line.
THE RECEIVE SECTION
The Receive Section receives a bipolar signal from
the line either via a 1:1 Transformer or a 0.01mF Ca-
pacitor. As the Receive Section receives this line sig-
nal it does the following:
Adjusts the signal level through an AGC circuit.
Optionally equalizes this signal for cable loss.
Attempts to quantify a bit-interval within the line sig-
nal as either a “1”, “-1” or a “0” by slicing this data.
This sliced data is used by the Clock Recovery PLL
to recover the timing element within the line signal.
The sliced data is routed to the HDB3/B3ZS
Decoder, during which the original data content as
transmitted by the Remote Terminal Equipment is
restored to its original content.
Outputs the recovered clock and data to the Local
Terminal Equipment in the form of CMOS level sig-
nals via the RPOS, RNEG, RCLK1 and RCLK2 out-
put pins.
THE MICROPROCESSOR SERIAL INTERFACE
The XRT7300 can be configured to operate in either
the Hardware Mode or the HOST Mode.
The Hardware Mode
Connect the HOST/HW input pin (pin 18) to GND to
configure the XRT7300 to operate in the Hardware
Mode.
When the XRT7300 is operating in the Hardware
Mode, the following is true:
1. The Microprocessor Serial Interface block is
disabled.
2. The XRT7300 is configured via input pin settings.
Each of the pins associated with the Microprocessor
Serial Interface takes on their alternative role as de-
fined in Table 1.
3. All of the remaining input pins become active.
TABLE 1: ROLE OF MICROPROCESSOR SERIAL INTERFACE PINS WHEN THE XRT7300 IS OPERATING IN THE
HARDWARE MODE
PIN #
PIN NAME
FUNCTION WHILE IN THE HARDWARE MODE
11
REGRESET/(RCLK2INV)
RCLK2INV
19
SDI/(LOSMUTEN)
LOSMUTEN
20
SDO/(LCV)
LCV
21
SCLK/(ENCODIS)
ENCODIS
22
CS/(DECODIS)
DECODIS
30
LCV/(RCLK2)
RCLK2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT7300IVTR-F | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT7302IV | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Transceiver |
| XRT73L00 | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L00A | 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT |
| XRT73L00AES | 功能描述:界面開發(fā)工具 Eval System for XRT73L00A Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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