參數(shù)資料
型號(hào): XRT7300IV
廠(chǎng)商: EXAR CORP
元件分類(lèi): 數(shù)字傳輸電路
英文描述: E3/DS3/STS-1 LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PQFP44
封裝: 10 X 10 MM, 1.40 MM HEIGHT, TQFP-44
文件頁(yè)數(shù): 43/55頁(yè)
文件大?。?/td> 608K
代理商: XRT7300IV
á
XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.1
39
Figure 30 illustrates the path that the data takes in the
XRT7300 when the chip is configured to operate in
the Remote Loop-Back Mode.
During Remote Loop-Back operation, any data which
is inputted via the RTIP and RRING input pins is also
outputted to the Terminal Equipment via the RPOS,
RNEG and RCLK output pins.
The XRT7300 can be configured to operate in the Re-
mote Loop-Back Mode by employing either one of the
following two steps
If the XRT7300 is operating in the HOST Mode:
Access the Microprocessor Serial Interface and write
a “1” into the RLB bit-field and a “0” in the LLB bit-field
in Command Register CR4.
If the XRT7300 is operating in the Hardware
Mode:
Set the RLB input pin (pin 15) to “High” and the LLB
input pin (pin 16) to “Low”.
F
IGURE
30. T
HE
R
EMOTE
L
OOP
-B
ACK
P
ATH
IN
THE
XRT7300
AGC/
Equalizer
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO/LCV
SCLK
CS
REGRESET
RTIP
RRING
REQDIS
RCLK1
RCLK2/LCV
RPOS
RNEG
DECODIS
RLOS
LLB
RLB
ENCODIS
TAOS
TPDATA
TNDATA
TCLK
RLOL EXCLK
Device
Monitor
MTIP
MRING
Transmit
Logic
Duty Cycle Adjust
TXLEV
TXOFF
DMO
TTIP
TRING
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Remote
Loop-Back Path
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X
STS-1/DS3
E3
LLB
RLB
X
X
X
0
1
相關(guān)PDF資料
PDF描述
XRT7300 E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線(xiàn)接口單元)
XRT73L02M TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02MIV TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02 2 Channel E3/DS3/STS-1 Line Interface Unit(2通道 E3/DS3/STS-1線(xiàn)接口單元)
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