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XRT72L50
SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
336
NOTE: This interrupt is only active if the XRT72L50 Framer IC has been configured to process the BIP-4 nibble within each
incoming and outbound E3 frame.
Enabling and Disabling the Detection of FEBE Event Interrupt
The user can enable or disable the Detection of BIP-4 Error’ interrupt by writing the appropriate value into Bit 2
(BIP-4 Interrupt Enable) within the Rx E3 Interrupt Enable Register - 2, as indicated below.
Setting this bit-field to “1” enables this interrupt. Conversely, setting this bit-field to “0” disables this interrupt.
Servicing the Detection of the BIP-4 Error Interrupt
Whenever the XRT72L50 Framer IC detects this interrupt, it will do the following.
It will assert the Interrupt Request output pin (Int), by driving it "High".
It will set the Bit 2 (BIP-4 Interrupt Status), within the RxE3 Interrupt Status Register - 2 as indicated below.
Whenever the Terminal Equipment encounters the Detection of BIP-4 Error Interrupt, it should do the following.
It should read the contents of the PMON Parity Error Event Count Registers (located at Addresses 0x54 and
0x55) in order to determine the number of BIP-4 Errors that have been received by the XRT72L50 Framer IC.
5.3.6.2.8
The Detection of Framing Error Interrupt
If the Detection of Framing Error Interrupt is enabled, then the XRT72L50 Framer IC will generate an interrupt,
anytime the Receive E3 Framer block has received an E3 frame with an incorrect FAS pattern value.
RxE3 Interrupt Enable Register - 2 (Address = 0x13)
BIT 7BIT 6BIT 5BIT 4BIT 3
BIT 2BIT 1BIT 0
Not Used
FERF
Interrupt
Enable
BIP-4 Error
Interrupt
Enable
Framing Error
Interrupt
Enable
Not Used
R/W
RO
R/W
RO
0
0000
X0
0
RxE3 Interrupt Status Register - 2 (Address = 0x15)
BIT 7BIT 6BIT 5BIT 4BIT 3
BIT 2BIT 1BIT 0
Not Used
FERF
Interrupt
Status
BIP-4
Error
Interrupt
Status
Framing
Error
Interrupt
Status
Not Used
RO
RUR
0
0000
100