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XRT72L50
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SINGLE CHANNEL DS3/E3 FRAMER WITH HDLC CONTROLLER
REV. 1.2.1
107
NOTE: This register is ignored if Bit 7 (Tx BIP-4 Enable) within the TxE3 Configuration register (Address = 0x30) is set to
“0”.
2.3.8
Performance Monitor Registers
2.3.8.1
PMON Line Code Violation Count Register - MSB
This Reset-upon-Read register, along with the PMON LCV Event Count Register - LSB (Address = 0x51)
contains a 16-bit representation of the number of Line Code Violations that have been detected by the Receive
DS3/E3 Framer block, since the last read of these registers. This register contains the MSB (or Upper-Byte)
value of this 16 bit expression.
2.3.8.2
PMON Line Code Violation Count Register - LSB
This Reset-upon-Read register, along with the PMON LCV Event Count Register - LSB (Address = 0x50)
contains a 16-bit representation of the number of Line Code Violations that have been detected by the Receive
DS3/E3 Framer block, since the last read of these registers. This register contains the LSB (or Lower-Byte)
value of this 16 bit expression.
2.3.8.3
PMON Framing Bit/Byte Error Count Register - MSB
This Reset-upon-Read register, along with the PMON Framing Bit/Byte Error Count Register - LSB (Address =
0x53) contains a 16-bit representation of the number of Framing Bit or Byte Errors that have been detected by
the Receive DS3/E3 Framer block, since the last read of these registers. This register contains the MSB (or
Upper-Byte) value of this 16 bit expression.
PMON LCV Event Count Register - MSB (Address = 0x50)
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
LCV Count - High Byte
RURRUR
RUR
RURRUR
00
000
PMON LCV Event Count Register - LSB (Address = 0x51)
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
LCV Count - Low Byte
RURRUR
RUR
RURRUR
00
000
PMON Framing Bit/Byte Error Count Register - MSB (Address = 0x52)
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
Framing Bit/Byte Error Count - High Byte
RURRUR
RUR
RURRUR
00
000