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參數(shù)資料
| 型號： | XRT7295ATIWTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RCVR DS3/SONET STS-1 20SOJ |
| 標準包裝： | 1,000 |
| 類型： | 接收器 |
| 驅動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | DS3，STS-1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-BSOJ |
| 供應商設備封裝： | 20-SOJ |
| 包裝： | 帶卷 (TR) |
XRT7295AT
11
Rev.1.20
JITTER ACCOMMODATION
Under all allowable operating conditions, the jitter
accommodation of the XRT7295AT device exceeds all
system
requirements
for
error-free
operation
(BER<1E-9). The typical (VDD = 5V, T = 25°C, DSX-3
nominal signal level) jitter accommodation for the
XRT7295AT is shown in Figure 10.
FALSE-LOCK IMMUNITY
False-lock is defined as the condition where a PLL
recovered clock obtains stable phase-lock at a frequency
not equal to the incoming data rate. The XRT7295AT
device uses a combination frequency/phase-lock
architecture to prevent false-lock. An on-chip frequency
comparator continuously compares the EXCLK reference
to the PLL clock. If the frequency difference between the
EXCLK and PLL clock exceeds approximately ±0.5%,
correction circuitry forces re-acquisition of the proper
frequency and phase.
ACQUISITION TIME
If a valid input signal is assumed to be already present at
RIN, the maximum time between the application of device
power and error-free operation is 20ms. If power has
already been applied, the interval between the application
of valid data (or the action of valid data following a loss of
signal) and error-free operation is 4ms.
LOSS-OF-LOCK DETECTION
As stated above, the PLL acquisition aid circuitry monitors
the PLL clock frequency relative to the EXCLK frequency.
The RLOL alarm is activated if the difference between the
PLL clock and the EXCLK frequency exceeds
approximately ±0.5%.
This will not occur until at least 250 bit periods after loss of
input data.
Figure 9. Typical PLL Jitter Transfer
Characteristic
1
0
-5
-4
-3
-2
-1
100
500 1K
5K 10K
50K100K 500K
PEAK = 0.05dB
f3dB = 205kHz
Frequency (Hz)
M
ag
n
it
u
d
e
R
es
p
o
n
se
(d
B
)
1
10
100
1K
10K
100K
1000K
40
10
1.0
0.1
XRT7295AT Typical
PUB 54014
G.824
TR-TSY-000499
Category 1
TR-TSY-000499
Category 2
5k
10
10k
5
60k
1
300k
0.5
1M
0.4
XRT7295AT Typical
Sinewave Jitter Frequency (Hz)
Figure 10. Input Jitter Tolerance at DSX-3 Level
Jitter
Frequency
(Hz)
Jitter
Amplitude
(U.I.)
P
ea
k-
P
ea
k
S
in
ew
av
e
Ji
tt
er
(U
.I.
)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT7295CTIW | 功能描述:總線接收器 DS3/E3/SONET STS-1 Line Receiver RoHS:否 制造商:Texas Instruments 接收機數(shù)量:4 接收機信號類型:Differential 接口類型:EIA/TIA-422-B, V.11 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-16 封裝:Reel |
| XRT7295CTIW-F | 功能描述:總線接收器 DS3/E3/SONET STS-1 Line Receiver RoHS:否 制造商:Texas Instruments 接收機數(shù)量:4 接收機信號類型:Differential 接口類型:EIA/TIA-422-B, V.11 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-16 封裝:Reel |
| XRT7295E | 制造商:EXAR 制造商全稱:EXAR 功能描述:INTEGRATED LINE RECEIVER |
| XR-T7295E | 制造商:EXAR 制造商全稱:EXAR 功能描述:INTEGRATED LINE RECEIVER |
| XR-T7295E-1EIP | 制造商:EXAR 制造商全稱:EXAR 功能描述:INTEGRATED LINE RECEIVER |
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