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參數(shù)資料
| 型號(hào)： | XRT7295AEIWTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 3/15頁 |
| 文件大小： | 0K |
| 描述： | IC E3 LINE RECEIVER 20SOJ |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 接收器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 0/1 |
| 規(guī)程： | E3 |
| 電源電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-BSOJ |
| 供應(yīng)商設(shè)備封裝： | 20-SOJ |
| 包裝： | 帶卷 (TR) |
XRT7295AE
11
Rev. 2.0.0
Note:
1
Recommended shield beads are the Fair-Rite
2643000101 or the Fair-Rite 2743019446 (surface
mount).
Figure 8. Recommended Power Supply
Bypassing Network
Receive Input
The connections to the receive input pin, RIN, must be
carefully considered. Noise-coupling must be mini-
mized along the path from the signal entering the board
to the input pin. Any noise coupled into the
XRT7295AE input directly degrades the signal-to-
noise ratio of the input signal.
PLL Filter Capacitor
The PLL filter capacitor between pins LPF1 and LPF2
must be placed as close to the chip as possible. The
LPF1 and LPF 2 pins are adjacent, allowing for short
lead lengths with no crossovers to the external capaci-
tor. Noise-coupling into the LPF1 and LPF2 pins may
degrade PLL performance.
Handling Precautions
Although protection circuitry has been design into this
device, proper precautions should be taken to avoid
exposure to Electrostatic Discharge (ESD) during han-
dling and mounting.
COMPLIANCE SPECIFICATIONS
Compliance with CCITT Recommendations G.703,
G.775, and G.824, 1988.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT7295AT | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3/Sonet STS-1 Integrated Line Receiver |
| XRT7295AT_10 | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3 SONET STS1 Integrated Line Receiver |
| XRT7295ATIW | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7295ATIW-F | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI -.5V--6.5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7295ATIW-F | 制造商:Exar Corporation 功能描述:T3/E3 LIU IC |
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