Rev. 2.0.0 Line Termination and Input Capacitance The recommended receive termination is shown in Figure 3. The 75 resistor termin" />
參數(shù)資料
型號: XRT7295AEIWTR-F
廠商: Exar Corporation
文件頁數(shù): 12/15頁
文件大?。?/td> 0K
描述: IC E3 LINE RECEIVER 20SOJ
標(biāo)準(zhǔn)包裝: 1,000
類型: 接收器
驅(qū)動器/接收器數(shù): 0/1
規(guī)程: E3
電源電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 20-BSOJ
供應(yīng)商設(shè)備封裝: 20-SOJ
包裝: 帶卷 (TR)
XRT7295AE
6
Rev. 2.0.0
Line Termination and Input Capacitance
The recommended receive termination is shown in
Figure 3. The 75
resistor terminates the coaxial cable
with its characteristic impedance. The 0.01
F capaci-
tor to R
IN couples the signal into the receive input
without disturbing the internally generated DC bias
level present on R
IN. The input capacitance at the RIN
pin is 2.8pF.
External Loop Filter Capacitor
Figure 3 shows the connection to an external 0.1
F
capacitor at the LPF1/LPF2 pins. This capacitor is part
of the PLL filter. A non-polarized, low-leakage capaci-
tor should be used. A ceramic capacitor with the value
0.1
F +/-20% is acceptable.
Figure 3. Receiver Configuration
TIMINGRECOVERY
Output Jitter
The total jitter appearing on the RCLK output during
normal operation consists of two components. First,
some jitter appears on RCLK because of jitter on the
incoming signal. (The following section discussed the
jitter transfer characteristic, which describes the rela-
tionship between input and output jitter.) Second, noise
sources within the XRT7295AE or noise sources that
are coupled into the device through the power supplies
create jitter on RCLK. The magnitude of this
XRT7295AE
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