
8
x r
PRELIMINARY
E3 UNI FOR ATM
XRT7234
REV. P1.0.0
Receiver IC) and the XR-T7296 (E3 Line Transmitter IC). Figure 1 presents an illustration of the “System-Level” interfac-
ing of the XR-T7234 E3 UNI, when the E3 line signal is transmitted over a copper medium.
Figure 1. System Level Interfacing of the XR-T7234 E3 UNI (E3 Data is transmitted over Copper Medium).
Additionally, the user would connect the single-rail output pin of the UNI (TxPOS) to the “Electrical” input of an
“Electrical to Optical” converter; and connect the single-rail input pin of the UNI (RxPOS) to the “Electrical” output
of an “Optical to Electrical” converter. The “Electrical to Optical” and “Optical to Electrical” converters are “entities”
that handle the translation between the electronic and photonic modes. Figure 2 presents an illustration of the “Sys-
tem Level” interfacing of the XR-T7234 E3 UNI, when the E3 line signal is transmitted over an optical medium.
The remainder of this text will frequently refer to each of these “entities” as:
The ATM Layer Processor
The Local Microprocessor
The Line Interface Unit (LIU) IC
1.2 Internal Operation of the XR-T7234 E3 UNI device
Whenever an ATM switch, that has access to an E3 line, needs to transmit ATM cell data to a “Far-End” Terminal over
the E3 line, it will write the ATM cell data into the Transmit Utopia Interface block of the XR-T7234 E3 UNI device.
Afterwards, the Transmit Utopia Interface block will ultimately write this cell data to an internal FIFO (referred to as
Tx FIFO throughout this document); where it can be read and further processed by the Transmit Cell Processor. The
Transmit Utopia Interface block will also perform some parity checking on the data that it receives from the ATM
Layer processor. Finally, the Transmit Utopia Interface block will provide signaling to support data-flow control
ATM
Layer
Processor
Line
Interface
Unit
Microprocessor
Interface
ALE_AS
XR-T7234
TxData
[15:0]
RxData
[15:0]
To/From
Far End
E3 UNI
TxPOS
TxNEG
RxPOS
RxNEG
ATM Switch
Local “Housekeeping” Processor
D[15:0] WRB_R
W
RDS_D
S
Rdy_Dtck
TxClav
RxClav
Transmit
Utopia
Interface
Block
Transmit
Cell
Processor
Transmit
E3
Framer
Receive
Cell
Processor
Receive
Utopia
Interface
Block
Receive
E3
Framer