參數(shù)資料
型號(hào)： XRT59L921IB
廠商： EXAR CORP
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT
中文描述： DATACOM, PCM TRANSCEIVER, PBGA316
封裝： 21 X 21 MM, STBGA-316
文件頁(yè)數(shù)： 26/32頁(yè)
文件大?。?/td> 377K
代理商： XRT59L921IB
XRT59L921
24
TWENTY-ONE CHANNEL E1 LINE INTERFACE UNIT
REV. 1.2.1
2.3
The Receive Equalizer Bock
After a given Channel (within the XRT59L921) has received the incoming line signal, via the RTIP_n and
RRing_n input pins, the first block that this signal will pass through is the Receive Equalizer block.
As the line signal is transmitted from a given Transmitting terminal, the pulse shapes (at that location) are
basically square. Hence, these pulses consist of a combination of low and high frequency Fourier components.
As this line signal travels from the transmitting terminal (via the coaxial cable or twisted pair) to the receiving
terminal, it will be subjected to frequency-dependent loss. In other words, the higher frequency components of
the signal will be subjected to a greater amount of attenuation than the lower frequency components. If this line
signal travels over reasonably long cable lengths, then the shape of the pulses (which were originally square)
will be distorted and with inter-symbol interference increases.
The purpose of this block is to equalize the incoming distorted signal, due to cable loss. In essence, the
Receive Equalizer block accomplishes this by subjecting the received line signal to frequency-dependent
amplification (which attempts to counter the frequency-dependent loss that the line signal has experienced). By
doing this, the Receive Equalizer is attempting to restore the shape of the line signal so that the received data
can be recovered reliably.
2.4
The Peak Detector and Slicer Block
After the incoming line signal has passed through the Receive Equalizer block, it will next be routed to the
Slicer block. The purpose of the Slicer block is to quantify a given bit-period (or symbol) within the incoming
line signal as either a “1” or a “0”.
2.5
The LOS Detector block
The LOS Detector block, within each channel (of the XRT59L921) was specifically designed to comply with the
LOS Declaration/Clearance requirements per ITU-T G.775. As a consequence, the channel will declare a LOS
Condition, (by driving the RxLOS output pin “High”) if the received line signal amplitude drops to –20dB or
below. Further, the channel will clear the LOS Condition if the signal amplitude rises back up to –15dB or
above.
Figure 13
presents an illustration that depicts the signal levels at which a given channel (within the
XRT59L921) will assert and clear LOS.
Timing Requirements associated with Declaring and Clearing the LOS Indicator. The XRT59L921 was
designed to meet the ITU-T G.775 specification timing requirements for declaring and clearing the LOS
F
IGURE
13. I
LLUSTRATION
OF
THE
S
IGNAL
L
EVELS
THAT
THE
R
ECEIVER
S
ECTIONS
(
WITHIN
XRT59L921)
WILL
DECLARE
AND
CLEAR
LOS
LOS Signal Must be Cleared
Minimum Cable Loss for E1
LOS Signal Must be Cleared or Declared
LOS Signal Must be Declared
0dB
-6dB
-9dB
-35dB
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