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| 型號： | XRT4500CV |
| 廠商： | EXAR CORP |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | MULTIPROTOCOL SERIAL NETWORK INTERFACE IC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80 |
| 文件頁數(shù)： | 58/99頁 |
| 文件大?。?/td> | 1384K |
| 代理商： | XRT4500CV |
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á
XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
55
In this case, the “2-Clock” Mode offers a considerable
amount of design flexibility. This approach permits the
“DCE Equipment” System Design Engineer to design
and layout a board that can be automatically config-
ured to support either the “3-Clock” Mode (if all three
clock signals are present, over the DTE/DCE Inter-
face). Further, this approach also permits the System
Design Engineer to configure the XRT4500 into the
“2-Clock” Mode (if the SCTE clock signal is not
present). This feature is a nice alternative to “hard-
wiring” the “TXC” output (of the DCE SCC) to the
“SCTE” input.
N
OTE
:
The “2-Clock” Mode feature, by itself, does not solve
the “2-Clock/Propagation Delay” phenomenon. However,
the “2-Clock” Mode, within the XRT4500, permits the user
to do the following.
a. To configure the XRT4500 to automatically operate
in the “3-Clock” Mode, whenever it is interfaced to a
DTE that supports all three (3) clock signals, or
b. To configure the XRT4500 to automatically operate
in the “2-Clock” Mode, whenever it is interfaced to a
DTE that only supports two (2) clock signals. Once
the user has configured the XRT4500 to operate in
the “2-Clock” Mode, then the user can “solve” the “2-
Clock/Propagation Delay” phenomenon by invoking
the “Clock Inversion” feature, as described below in
Section 1.2.6.
Configuring the “2-Clock” Mode.
The user can configure the XRT4500 to operate in
the “2-Clock” Mode by setting the “2CK/3CK” input
pin “high”. Conversely, the user can disable the “2-
Clock” Mode (otherwise known as operating the
XRT4500 in the “3-Clock” Mode) by setting the “2CK/
3CK” input pin “l(fā)ow”.
1.3.6
The “Clock Inversion” (CK_INV) feature
The XRT4500 can be configured to invert the “TXC”
signal by setting the “CK_IN” input pin (pin 54) “l(fā)ow”.
Setting the “CK_INV” input to “high” removes the in-
vert from the “TXC” signal path. An illustration of the
“DCE Mode” XRT4500, configured to invert the “TXC”
signal is illustrated in Figure 28.
F
IGURE
27. I
LLUSTRATION
OF
THE
DCE/DTE I
NTERFACE
,
WITH
THE
DCE M
ODE
XRT4500
OPERATING
IN
THE
“2-
C
LOCK
” M
ODE
DCE
SCC (L)
XRT4500
XRT4500
RX1
TX1
RX2
TX2
RX3
TX3
RX2
TX2
RX1
TX1
RXD
RXC
TXC
SCTE_IN
TXD_IN
TXD
SCTE
TXC_IN
RXC_IN
RXD_IN
60
67
73
74
1
78
79
77
76
70
71
64
65
63
62
1
74
68
67
60
63
62
64
65
70
71
77
76
78
79
TXD
TXC
RXC
RXD
SCC (R)
DTE
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