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參數(shù)資料
| 型號(hào)： | XRT4500CV |
| 廠商： | EXAR CORP |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | MULTIPROTOCOL SERIAL NETWORK INTERFACE IC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-80 |
| 文件頁數(shù)： | 12/99頁 |
| 文件大?。?/td> | 1384K |
| 代理商： | XRT4500CV |
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XRT4500
MULTIPROTOCOL SERIAL NETWORK INTERFACE IC
REV. 1.0.7
9
PIN DESCRIPTIONS (CONT.)
PIN
#
Signal
DTE
MODE
DCE
MODE
TYPE
FUNCTION
23
RX8D
D_RI
D_RL
O
Receiver 8 – Digital Data Output to Terminal Equipment
The XRT4500 receives a line signal (in either the V.10 or V.28
manner) via the RX8I input pin (Pin 25). The XRT4500 then con-
verts this data into a digital format (e.g., a CMOS level binary
data stream) and outputs it via this pin. The exact functionality of
this output pin depends upon whether the XRT4500 is operating
in the DCE or DTE Modes.
DCE Mode – Remote Loop-back Indicator Output
If the XRT4500 has been configured to operate in the DCE
Mode –
This output pin should be connected to the “RL” (Remote
Loop-back) indicator input pin (of the Terminal Equipment).
DTE Mode – Ring Indicator (or Test Mode Indicator) Output
If the XRT4500 has been configured to operate in the DTE
Mode –
This output pin should be connected to either the “RI”
(Ring Indicator) or “TM” (Test Mode) input pin of the Terminal
Equipment.
Notes:
This output pin is tri-stated if the EN_OUT* input pin (pin
48) is “HIGH”. If the XRT4500 has been configured to operate in
the “Registered” Mode, then data will be outputted via this pin,
upon the rising edge of the REG_CLK clock signal.
24
REG
I
Register Mode Control Select Input Pin:
This input pin permits the user to configure the XRT4500 to
operate in either the “Registered” Mode or in the “non-Regis-
tered” Mode. If the XRT4500 has been configured to operate in
the “Registered” Mode, then the following will happen.
Data at the “TX5D” and “TX8D” input pins (Pins 15 & 17) will
be latched into the XRT4500 circuitry upon the rising edge of
the clock signal applied at the “REG_CLK” input pin.
Data will be output via the “RX5D” and “RX8D” pins, upon the
rising edge of the clock signal applied at the “REG_CLK” input
pin.
If the XRT4500 has been configured to operate in the “Non-Reg-
istered” Mode, then the “REG_CLK” clock signal will have no
effect on the processing of signals via the “TX5D”, “TX8D”,
“RX5D” and “RX8D” pins.
Setting the “REG” input to “HIGH” configures the XRT4500 to
operate in the “Registered” Mode.
Setting the “REG” input to “LOW” configures the XRT4500 to
operate in the “Non-Registered” Mode.
This pin contains an internal 20K
pull-down to ground.
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