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參數(shù)資料
| 型號(hào)： | XRK69774CR |
| 廠商： | EXAR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 1:14 LVCMOS PLL CLOCK GENERATOR |
| 中文描述： | 69774 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, LQFP-52 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 84K |
| 代理商： | XRK69774CR |
XRK69774
PRELIMINARY
8
1:14 LVCMOS PLL CLOCK GENERATOR
REV. P1.0.1
F
IGURE
4. O
UTPUT
-
TO
-
OUTPUT
S
KEW
t
SK(O)
F
IGURE
5. P
ROPOGATION
DELAY
(t
()
,
STATIC
PHASE
OFFSET
)
TEST
REFERENCE
F
IGURE
6. O
UTPUT
D
UTY
C
YCLE
(DC)
F
IGURE
7. I/O J
ITTER
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device.
V
CC
V
CC
÷2
GND
V
CC
V
CC
÷2
GND
t
SK(O)
FB_IN
t
()
CCLKx
V
CC
V
CC
÷2
GND
V
CC
V
CC
÷2
GND
tp
T
0
DC=t
P
/T
0
x 100%
The time from the PLL controlled edge to the non controlled edge, divided
by the time between PLL controlled edges, expressed as a percentage
V
CC
V
CC
÷2
GND
FB_IN
CCLKx
T
JIT(I/O)
= |T
0
-T
1
mean |
The deviation in t
0
for a controlled edge with respect to a t
0
mean in a random
sample of cycles
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRK69774IR | 1:14 LVCMOS PLL CLOCK GENERATOR |
| XRK697H73 | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK697H73CR | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK697H73IR | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK7933 | INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRK69774IR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:14 LVCMOS PLL CLOCK GENERATOR |
| XRK697H73 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK697H73CR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK697H73IR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK7933 | 制造商:EXAR 制造商全稱:EXAR 功能描述:INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER |
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