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參數(shù)資料
| 型號： | XRK69773 |
| 廠商： | Exar Corporation |
| 英文描述： | 1:12 LVCMOS PLL CLOCK GENERATOR |
| 中文描述： | 1:12的LVCMOS PLL時鐘發(fā)生器 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 98K |
| 代理商： | XRK69773 |
PRELIMINARY
XRK69773
3
REV. P1.0.0
PIN DESCRIPTIONS
1:12 LVCMOS PLL CLOCK GENERATOR
* 25K
Ω
pull-up resistor
P
IN
#
N
AME
T
YPE
D
ESCRIPTION
1, 15, 24, 30,
35, 39, 47, 51
GND
POWER
Power supply ground
2
MR/OE
INPUT*
Master reset and output enable. High = output enabled, Low = device
reset & outputs tri-stated
3
STOP_CLK
INPUT*
Clock input for serial control.
4
STOP_DATA
INPUT*
Data input for serial control
5, 26, 27
FSEL_FB[2:0]
INPUT*
Select inputs for control of feedback divide value.
6
PLL_EN
INPUT*
PLL bypass. High = PLL, Low = PLL bypass
7
REF_SEL
INPUT*
Xtal or CLK select. High = Xtal input selected, Low = CLK0 or CLK1
selected
8
CLK_SEL
INPUT*
CLK0 or CLK1 Select. High = CLK1 selected, Low= CLK0 selected
9
10
CLK0
CLK1
INPUT*
INPUT*
PLL Reference Clock Inputs
11
12
PECL
PECL
INPUT
Diffferential LVPECL Clock Input
13
VDD_PLL
POWER
Analog supply for PLL
14
INV_CLK
INPUT*
Invert clock select for QC3 & QC2. High = invert, Low = normal operation
16, 18, 21, 23
QC[3:0]
OUTPUT
Clock outputs (Bank C)
17, 22, 33,
37, 45, 49
VDD
POWER
Power supply for outputs.
19,20
FSEL_C[1:0]
INPUT*
Bank C divide select pins.
25
QSYNC
OUTPUT
Synchronization output for Bank A and Bank C.
28
VDD
POWER
Power supply for core
29
QFB
OUTPUT
Feedback clock output
31
FB_IN
INPUT*
Feedback input
32, 34 ,36 ,38
QB[3:0]
OUTPUT
Clock outputs (Bank B)
40, 41
FSEL_B[1:0]
INPUT*
Bank B divide select pins.
42, 43
FSEL_A[1:0]
INPUT*
Bank A divide select pins.
44, 46, 48, 50
QA[3:0]
OUTPUT
Clock outputs (Bank A)
52
VCO_SEL
INPUT*
VCO select. High = VCO/1, Low = VCO/2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRK69773CR | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69773IR | 1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69774 | 1:14 LVCMOS PLL CLOCK GENERATOR |
| XRK69774CR | 1:14 LVCMOS PLL CLOCK GENERATOR |
| XRK69774IR | 1:14 LVCMOS PLL CLOCK GENERATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRK69773CR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69773IR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:12 LVCMOS PLL CLOCK GENERATOR |
| XRK69774 | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:14 LVCMOS PLL CLOCK GENERATOR |
| XRK69774CR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:14 LVCMOS PLL CLOCK GENERATOR |
| XRK69774IR | 制造商:EXAR 制造商全稱:EXAR 功能描述:1:14 LVCMOS PLL CLOCK GENERATOR |
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