參數資料
| 型號： | XRD98L62ACV-F |
| 廠商： | Exar Corporation |
| 文件頁數： | 16/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD DIGITIZER 12BIT 48TQFP |
| 標準包裝： | 250 |
| 位數： | 12 |
| 通道數： | 1 |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數字： | 2.7 V ~ 3.6 V |
| 封裝/外殼： | 48-TQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
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23
Rev. P2.00
XRD98L62
Preliminary
Calibration Options
Fast Cal
The purpose of this option is to reduce the amount of
time required for initial convergence of the calibration
feedback system. The feedback system is designed to
have a slow response time to avoid introducing image
artifacts. The slow response time is achieved by
averaging many OB pixels and by limiting the Fine
accumulator changes to ± 1 count at a time (FDAC lsb
= ADC lsb). The FastCal option maintains this slow
response while the difference between the averaged
ADC data and the Offset Code is small, but when the
difference is larger than ±128 lsb’s the coarse accumu-
lator takes a step. The actual step size depends on the
PGA Gain code, and is set such that the step will cause
no more than a 128 LSB change in the ADC output.
To activate the FastCal mode write a “1” to the FastCal
bit in the Calibration register. By default the FastCal
mode is active.
Difference [ADC lsb's]
Offset
Adjustment
[ADC
LSBs]
0
-1
+1
-128
+128
0
+0.5
-0.5
Fine DAC Steps
Coarse DAC steps
Figure 10. Calibration in FastCal
(Speed Up) Mode
DNS[1]
DNS[0]
DNS Filter Width
0
OFF (default)
01
Narrow
1
0
Medium
11
Wide
Digital Noise Suppression (DNS Filter)
The purpose of this option is to eliminate small
changes in the Black Level offset by making the
calibration system less sensitive to small changes in
the measured offset. In this mode the user has the
option of selecting from three filter settings, see Table 4.
Table 4. DNS Threshold Programming
To activate the Digital Noise Suppression mode write
to the DNS[1:0] bits in the Calibration register.
By default the Digital Noise Suppression is ON, and
set to the wide filter width.
Hold Mode
The purpose of this mode is to prevent any changes in
the Fine or Coarse accumulators. This mode is in-
tended to optimize digital still camera applications
(DSC). The idea is to first run the calibration normally
so the Fine and Coarse accumulators converge on the
correct values to achieve the programmed Offset
Code. Then, just before acquiring the final image data,
activate the Hold mode. This will ensure the black level
offset of the CDS/PGA does not change while the final
image is being transferred out of the CCD. Once the
image has been acquired from the CCD, turn off the
Hold mode so the chip can continue to compensate for
any changes in offset due to temperature drift or other
effects.
To activate the Hold mode write a “1” to the CAL Hold
bit in the Calibration register. By default the Hold
mode is not active.
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相關代理商/技術參數 |
參數描述 |
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| XRD98L62EVAL | 功能描述:數據轉換 IC 開發(fā)工具 XRD98L62 EVAL BOARD RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L62ZEVAL | 功能描述:數據轉換 IC 開發(fā)工具 Eval Board (Solder) XRD98L62AIV RoHS:否 制造商:Texas Instruments 產品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| XRD98L63 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L63AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L63AIV-F | 功能描述:模數轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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