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參數(shù)資料
| 型號(hào)： | XRD8799AIQ |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 2MSPS 44PQFP |
| 產(chǎn)品變化通告： | Obsolescence Notification 15/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 功率耗散（最大）： | 450mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-PQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | * |
xr
xr
XRD8799
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.00
12
FIGURE 10. RELATIONSHIP OF DATA TO CLOCK
1.3
ANALOG INPUT
The XRD8799 has very flexible input range character-
istics. The user may set VREF(+) and VREF(-) to two
fixed voltages and then vary the input DC and AC lev-
els to match the VREF range. Another method is to
first design the analog input circuitry and then adjust
the reference voltages for the analog input range.
One advantage is that this approach may eliminate
the need for external gain and offset adjust circuitry
which may be required by fixed input range A/Ds.
The XRD8799's performance is optimized by using
analog input circuitry that is capable of driving the AIN
input. Figure 11 shows the equivalent circuit for AIN.
FIGURE 11. ANALOG INPUT EQUIVALENT CIRCUIT
1.4
ANALOG INPUT MULTIPLEXER
The XRD8799 includes a 8-Channel analog input
multiplexer. The relationship between the clock, the
multiplexer address, the WR and the output data is
shown in Figure 12.
FIGURE 12. MUX ADDRESS TIMING
FIGURE 13. ANALOG MUX TIMING
1.5
REFERENCE VOLTAGES
The input/output relationship is a function of VREF:
AIN = VIN - VREF(-)
VREF = VREF(+) - VREF(-)
DATA = 1024 * (AIN/VREF)
A system can increase total gain by reducing VREF.
CLOCK
DATA
b. Single sampling
N
BALANCE
CLOCK
DATA
a. Continuous sampling
N
N+1
N
N+1
50
10 pF
AV
DD
A
IN
80
φS
10 pF
160
4
1 pF
10 pF
Channel
Selection
8
Control
R Series
200
R MUX
200
1/2 [ V
REF(+)
+ V
REF(-)
]
φS
φB
1 pF
+
WR
Clock
DB0-DB9
t
CLKS2
t
WR
t
CLKH2
Address
t
AS
t
AH
Sample N
Old Address
Sample M
New Address
Sample
M+1
N-2 Valid
N-1 Valid
Old Address
N Valid
Old Address
M Valid
New Address
Note: t
CLKS2 = tCLKH2 = 0
A2, A1, A0
MUXEN
(Internal Signal)
t
AS
t
AH
WR
t
WR
t
MUXEN1
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