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參數(shù)資料
| 型號： | XRD8799AIQ |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 24/24頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 2MSPS 44PQFP |
| 產(chǎn)品變化通告： | Obsolescence Notification 15/Apr/2010 |
| 標準包裝： | 160 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 2M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 8 |
| 功率耗散（最大）： | 450mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應商設備封裝： | 44-PQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | * |
XRD8799
xr
LOW POWER, 2 MSPS, 10-BIT, A/D CONVERTER WITH 8-CHANNEL MUX
REV. 1.00
9
FIGURE 3. XRD8799 TIMING DIAGRAM
THEORY OF OPERATION
1.0
ANALOG-TO-DIGITAL CONVERSION
The XRD8799 converts analog voltages into 1024
digital codes by encoding the outputs of coarse and
fine comparators. Digital logic is used to generate the
overflow bit. The conversion is synchronous with the
clock and it is accomplished in 2 clock periods.
The reference resistance ladder is a series of resis-
tors. The fine comparators use a patented interpola-
tion circuit to generate the equivalent of 1024 evenly
spaced reference voltages between VREF(-) and
VREF(+).
The clock signal generates the two internal phases,
φB (CLK high) and φS (CLK low = sample) (See Fig-
ure 1). The rising edge of the CLK input marks the
end of the sampling phase (
φS). Internal delay of the
clock circuitry will delay the actual instant when
φS
disconnects the latches from the comparators. This
delay is called aperture delay (tAP).
The coarse comparators make the first pass conver-
sion and selects a ladder range for the fine compara-
tors. The fine comparators are connected to the se-
lected range during the next
φB phase.
FIGURE 4. XRD8799 COMPARATORS
AIN Sampling, Ladder Sampling, and Conversion
Timing
Figure 3 shows this relationship as a timing chart. AIN
sampling, ladder sampling and output data relation-
ships are shown for the general case where the levels
which drive the ladder need to change for each sam-
pled AIN time point. The ladder is referenced for both
last AIN sample and next AIN sample at the same
time. If the ladder's levels change by more than 1
LSB, one of the samples must be discarded. Also
note that the clock low period for the discarded AIN
can be reduced to the minimum tS time.
Auto
Balance
CLOCK
Data
Analog
Input
Sample
N-1
Sample
N
Sample
N+1
Auto
Balance
N-1
T
S
V
IH
V
IL
V
OH
V
OL
t
F
t
B
t
R
t
S
t
DL
t
HLD
t
AP
φ S
B
φ
B
φ
S
φ
Latch
Ref
Ladder
COARSE COMPARATOR
S
B
φ
Latch
Selected
Range
FINE COMPARATOR
VIN
VTAP
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