XRD64L43 11 Rev. P1.00 Differential Inputs The XRD64L43 can be used in either differential or single-ended input mode. For sing" />
參數(shù)資料
型號(hào): XRD64L43AIV-F
廠商: Exar Corporation
文件頁(yè)數(shù): 3/20頁(yè)
文件大小: 0K
描述: IC ADC 10B PAR 40MSPS DL 64LQFP
標(biāo)準(zhǔn)包裝: 160
位數(shù): 10
采樣率(每秒): 40M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 365mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤(pán)
輸入數(shù)目和類(lèi)型: 2 個(gè)單端,單極;2 個(gè)差分,單極
其它名稱(chēng): 1016-1638
XRD64L43AIV-F-ND
Preliminary
XRD64L43
11
Rev. P1.00
Differential Inputs
The XRD64L43 can be used in either differential or
single-ended input mode. For single-ended inputs, see
the Single-Ended Inputs Section. Differential inputs
reduce system noise by removing noise components
common at both input pins. Figure 5. is a simplified
diagram that is used as a common test circuit with our
XRD64L43ES application board. This circuit is used to
evaluate the dynamic performance of the XRD64L43
using differential inputs. Pin 16, DIFF should be held
high to select differential inputs.
Input A
Input B
VINA(+)
VCMO
VINA(-)
VINB(+)
VINB(-)
50
22
Transformer
Figure 5. Common Test Circuit for the
Differential Input Mode
SYNCO, Data Valid Delay and Latency
SYNCO is an output pin provided by the XRD64L43.
Valid data is available on the rising edge of SYNCO,
see Figure 6. The Latency for the XRD64L43 is 17
clock cycles.
Figure 6. SYNCO, Data Valid Delay and Latency
for the XRD64L43
Auto-Calibration
The XRD64L43 incorporates an auto-calibration cir-
cuit which continuously adjusts and matches the
offset and linearity of each ADC. This auto-calibra-
tion circuit is transparent to the user after the initial
4.2ms calibration (168,000 initial clock cycles).
Note: To avoid auto-calibration after power down, do
not disable CKIN. CKIN can be slowed down significantly
to save power without losing calibration.
CKIN
SYNCO
Valid Data
N
N-16
N-17
N-15
N+1
N+2
t
den=20ns
t
synco=2ns (typical)
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