參數(shù)資料
型號(hào): XR88C681CP/40-F
廠商: Exar Corporation
文件頁數(shù): 58/101頁
文件大?。?/td> 0K
描述: IC UART CMOS DUAL 40PDIP
標(biāo)準(zhǔn)包裝: 9
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 1 字節(jié),3 字節(jié)
電源電壓: 4.75 V ~ 5.25 V
帶并行端口:
帶CMOS:
安裝類型: 通孔
封裝/外殼: 40-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 40-PDIP
包裝: 管件
其它名稱: 1016-1328-5
XR88C681
6
Rev. 2.11
44 PLCC
40 PDIP,
CDIP
28 PDIP
Symbol
Type
Description
30
27
OP4
(RXRDY/
FFULL_A)
O
Output 4 (General Purpose Output).
This output pin
can also be programmed to function as the open-drain,
active-low, “Receiver Ready” or “FIFO Full” indicator
output for Channel A. (-RXRDY_A/-FFULL_A)
31
28
OP2
(TXCA_16)
(TXCA-1X)
(RXCA_1X)
O
Output 2 (General Purpose Output).
This output pin
can also be programmed to function as any of the fol-
lowing: The Channel A Transmitter 16X or 1X clock
output (TXCA_16X or TXCA_1X), or the Channel A
Receiver 1X clock output (RXCA_1X).
32
29
20
OP0
(-RTSA)
O
Output 0 (General Purpose Output).
This output pin
can also be programmed to function as the active-low,
Request-to-Send output for Channel A (-RTSA).
33
30
21
TXDA
O
Transmitter Serial Data Output (Channel A).
The
least significant bit of the character is transmitted first.
This output is held in the marking (high) state when the
transmitter is idle, disabled, or operating in the Local
LOOPBACK mode. If an external transmitter clock is
specified, TXCA, the data is shifted out of the TSR
(Transmitter Shift Register) on the falling the edge of
the clock.
34
NC
No Connect.
35
31
22
RXDA
I
Receive Serial Data Input (Channel A).
The least
significant bit of the character is received first. If an
external receiver clock, RXCA, is specified, the data is
sampled on the rising edge of the clock.
36
32
23
X1/CLK
I
Crystal Output of External Clock Input.
This pin is
the connection for one side of the crystal and a capaci-
tor to ground when the internal oscillator is used. If the
oscillator is not used, an external clock signal must be
supplied at this input.
In order for the XR88C681 device to function properly,
the user must supply a signal with frequencies be-
tween 2.0MHz and 4.0MHz. This requirement can be
met by either a crystal oscillator or by the external
TTL-compatible clock signal.
37
33
24
X2
O
Crystal Input.
Connection for the one side of the crys-
tal (opposite of X1/CLK). If the oscillator is used, a
capacitor must also be connected from this pin to
ground. This pin must be left open if an external clock
is supplied at X1/CLK.
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