REV. 1.1.1 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 4.6 Line Control Register (LCR) - Read/Write The Line Co" />
參數(shù)資料
型號(hào)： XR68M752IL-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 25/54頁(yè)
文件大小： 0K
描述： EVAL BOARD FOR XR68M752 32QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16M752/XR68M752
31
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
4.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
WORD LENGTH
0
5
0
1
6 (default)
1
0
7
1
8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
WORD
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1
5
1-1/2
1
6,7,8
2 (default)
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 11 for parity selection summary below.
Logic 0 = No parity.
Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR bit-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
BIT-1
BIT-0
BIT-2
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