- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16523 > XR68M752IL-0B-EB (Exar Corporation)EVAL BOARD FOR XR68M752 32QFN PDF資料下載
參數(shù)資料
| 型號(hào)： | XR68M752IL-0B-EB |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 24/54頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR68M752 32QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
XR16M752/XR68M752
30
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.1.1
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)
(logic 0 = default, TX trigger level = 8)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of spaces in the FIFO is above the selected trigger level, or when it gets empty in case that the FIFO
did not get filled over the trigger level on last re-load. Table 10 shows the selections. The UART will issue a
transmit interrupt when the number of available spaces in the FIFO is less than the transmit trigger level.
Table 10 shows the selections.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level = 8)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO is greater than the receive trigger level or when a receive data
timeout occurs (see “Section 2.10, Receiver” on page 17).
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
BIT-7
BIT-6
BIT-5
BIT
-4
RECEIVE
TRIGGER LEVEL
(CHARACTERS)
TRANSMIT
TRIGGER LEVEL
(SPACES)
0
1
0
1
0
1
0
1
0
1
0
1
8
16
56
60
8
16
32
56
FCR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LBR2518T101M | INDUCTOR WOUND 100UH 80MA 1007 |
| VE-JVY-EZ-S | CONVERTER MOD DC/DC 3.3V 16.5W |
| XR16V2752IL-0B-EB | EVAL BOARD FOR V2752 32QFN |
| EEU-FR1J271L | CAP ALUM 270UF 63V 20% RADIAL |
| UPA0J561MPD1TD | CAP ALUM 560UF 6.3V 20% RADIAL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR68M752IL32 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
| XR68M752IL32-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR68M752IL32TR-F | 功能描述:UART 接口集成電路 W/64 BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR68M752IM-0B-EB | 功能描述:界面開發(fā)工具 Support XR68M752 48L TQFP, PCI Interface RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| XR68M752IM48 | 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 64-BYTE FIFO |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。