REV. 1.4.0 3.0 REGISTER SET DESCRIPTION The internal register set of the V1410 consists of 3 different bl" />
參數(shù)資料
型號(hào): XR21V1410IL16TR-F
廠商: Exar Corporation
文件頁數(shù): 6/30頁
文件大?。?/td> 0K
描述: IC USB UART FIFO FULL SPD 16QFN
產(chǎn)品培訓(xùn)模塊: XR21V141x Full-Speed USB UART Family
標(biāo)準(zhǔn)包裝: 3,000
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 128 字節(jié),384 字節(jié)
規(guī)程: USB 2.0
電源電壓: 2.97 V ~ 3.63 V
帶自動(dòng)流量控制功能:
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN-EP(3x3)
包裝: 帶卷 (TR)
配用: 1016-1299-ND - EVAL BOARD FOR XR21V1410IL
XR21V1410
14
1-CH FULL-SPEED USB UART
REV. 1.4.0
3.0
REGISTER SET DESCRIPTION
The internal register set of the V1410 consists of 3 different blocks of registers: the UART Manager, UART
registers and UART miscellaneous registers. The UART Manager controls the TX and RX enables and FIFOs
of all UART channels. The UART registers configure and control the remaining UART channel functionality
with the exception of low latency mode, wide mode and custom interrupt packet enables in the UART custom
register block.
Registers are accessed only via the USB interface by the XR_SET_REG and XR_GET_REG commands listed
in Table 4. The register address offsets are given in Table 6, Table 7 and Table 15, and the register blocks
are given in Table 5.
3.1
UART Manager Registers
3.1.1
FIFO_ENABLE Registers
Enables the RX FIFO and TX FIFOs. For proper functionality, the UART TX and RX must be enabled in the
following order:
FIFO_ENABLE = 0x1
// Enable TX FIFO
UART_ENABLE = 0x3
// Enable TX and RX
FIFO_ENABLE = 0x3
// Enable RX FIFO
3.1.2
RX_FIFO_RESET and TX_FIFO_RESET Registers
Writing a non-zero value to these registers resets the FIFOs.
TABLE 6: UART MANAGER REGISTERS
ADDRESS
REGISTER NAME
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
0X10
FIFO_ENABLE
0
RX
TX
0X18
RX_FIFO_RESET
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
0x1C
TX_FIFO_RESET
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
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