REV. 1.4.0 1-CH FULL-SPEED USB UART 3.3.15 GPIO_SET Register Description (Read/Write) Writing a ’1’ in this register drives the GP" />
參數(shù)資料
型號: XR21V1410IL16TR-F
廠商: Exar Corporation
文件頁數(shù): 16/30頁
文件大?。?/td> 0K
描述: IC USB UART FIFO FULL SPD 16QFN
產(chǎn)品培訓(xùn)模塊: XR21V141x Full-Speed USB UART Family
標(biāo)準(zhǔn)包裝: 3,000
特點: *
通道數(shù): 1,UART
FIFO's: 128 字節(jié),384 字節(jié)
規(guī)程: USB 2.0
電源電壓: 2.97 V ~ 3.63 V
帶自動流量控制功能:
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN-EP(3x3)
包裝: 帶卷 (TR)
配用: 1016-1299-ND - EVAL BOARD FOR XR21V1410IL
XR21V1410
23
REV. 1.4.0
1-CH FULL-SPEED USB UART
3.3.15
GPIO_SET Register Description (Read/Write)
Writing a ’1’ in this register drives the GPIO output high. Writing a ’0’ to a bit has no effect. Bits 7-6 are unused
and should be ’0’.
3.3.16
GPIO_CLEAR Register Description (Read/Write)
Writing a ’1’ in this register drives the GPIO output low. Writing a ’0’ to a bit has no effect. Bits 7-6 are unused
and should be ’0’.
3.3.17
GPIO_STATUS Register Description (Read-Only)
This register reports the current state of the GPIO pin.
3.4
UART Custom Registers
3.4.1
CUSTOM Register Description (Read/Write)
This register controls the bMaxPacketSize and enables the Wide mode functionality for the UART.
CUSTOM[0]: Enable wide mode
Logic 0 = Normal (7, 8 or 9 bit data) mode
Logic 1 = Wide mode - See “Section 1.5.1.1, Wide Mode Transmit” on page 7, “Section 1.5.2.3, Wide
mode receive operation with 7 or 8-bit data” on page 8
and “Section 1.5.2.4, Wide mode receive
operation with 9-bit data” on page 8.
CUSTOM[1]: Max Packet Size
Logic 0 = bMaxPacketSize = 64 bytes
Logic 1 = bMaxPacketSize = 63 bytes (this bit is automatically set to ’1’ if the XR21V1410 receives a
CDC_ACM USB command)
CUSTOM[7:2]: Reserved
These bits are reserved and should remain ’0’
3.4.2
LOW_LATENCY Register Description (Read/Write)
This register is automatically set to logic ’1’ for baud rates below 46921 bps, and can be manually set for baud
rates of 46921 bps and higher. This register enables the Low latency feature of the UART. Write to this
register following any desired baud rate setting change.
LOW_LATENCY[0]: Enable Low Latency mode
Logic 0 = Receive data is not forwarded from the Rx FIFO until bMaxPacketSize (64 bytes) or timeout (3
characters) has occurred.
Logic 1 = All data in the RX FIFO is provided to the USB host at the next BULK IN request irrespective of the
number of bytes in the FIFO.
LOW_LATENCY[7:1]: Reserved
These bits are reserved and should remain ’0’.
TABLE 15: UART CUSTOM REGISTERS
ADDRESS
REGISTER NAME
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
0X03
CUSTOM
0
MaxPkt-
Size
WIDE_
En
0x04
LOW_LATENCY
0
EN
0x06
CUSTOM_INT_PACKET
0
GPIO5
GPIO4
GPIO3
GPIO0
0
GPIO2
GPIO1
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