REV. 1.0.0 I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 1.16.1 RS-485 Setup Time By default, the RTS# pin is asse" />
參數(shù)資料
型號： XR20M1280IL40-F
廠商： Exar Corporation
文件頁數(shù)： 16/63頁
文件大?。?/td> 0K
描述： IC UART I2C/SPI 128 BYTE 40QFN
產(chǎn)品培訓模塊： UART Product Overview
XR21V141x Full-Speed USB UART Family
標準包裝： 490
通道數(shù)： 1，UART
FIFO's： 128 字節(jié)
規(guī)程： RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤
供應商設備封裝： 40-QFN 裸露焊盤（6x6）
包裝： 托盤
其它名稱： 1016-1385
XR20M1280
23
REV. 1.0.0
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
1.16.1
RS-485 Setup Time
By default, the RTS# pin is asserted immediately before there is data on the TX output pin. For faster baud
rates, it may be possible that data is lost due to a long start-up time for an RS-485 transceiver. The M1280 can
delay the data from 0-15 bit times to allow the RS-485 transceiver to start up (See ”Section , SHR[7:4]: RS-
1.16.2
RS-485 Turn-Around Delay
At the end of sending data, the RTS# pin is de-asserted immediately after the TX pin goes idle. The RTS# pin
can be programmed to delay the RTS# from being asserted from 0-15 bit times (See ”Section , SHR[3:0]: RS-
485 Turn-Around Delay / Auto RTS Hysteresis” on page 40.). The delay optimizes the time needed for the
last transmission to reach the farthest station on a long cable network before switching off the line driver.
1.17
Normal Multidrop (9-bit) Mode - Receiver
Normal multidrop mode is enabled when SFR[6] = 1 (requires EFR[4] = 1) and EFR[5] = 0 (Special Character
Detect disabled). The receiver is set to Force Parity 0 (LCR[5:3] = ’111’) in order to detect address bytes.
With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an address byte is received
(parity bit = 1). This address byte will cause the UART to set the parity error. The UART will generate an LSR
interrupt and place the address byte in the RX FIFO. The software then examines the byte and enables the
receiver if the address matches its slave address, otherwise, it does not enable the receiver.
If the receiver has been enabled, the receiver will receive the subsequent data. If an address byte is received,
it will generate an LSR interrupt. The software again examines the byte and if the address matches its slave
address, it does not have to do anything. If the address does not match its slave address, then the receiver
should be disabled.
1.17.1
Auto Address Detection - Receiver
Auto address detection mode is enabled when SFR[6] = 1 (requires EFR[4] = 1) and EFR bit-5 = 1. The
desired slave address will need to be written into the XOFF2 register. The receiver will try to detect an address
byte that matches the porgrammed character in the XOFF2 register. If the received byte is a data byte or an
address byte that does not match the programmed character in the XOFF2 register, the receiver will discard
these data.
Upon receiving an address byte that matches the XOFF2 character, the receiver will be
automatically enabled if not already enabled, and the address character is pushed into the RX FIFO along with
the parity bit (in place of the parity error bit). The receiver also generates an LSR interrupt. The receiver will
then receive the subsequent data. If another address byte is received and this address does not match the
programmed XOFF2 character, then the receiver will automatically be disabled and the address byte is
ignored. If the address byte matches XOFF2, the receiver will put this byte in the RX FIFO along with the parity
bit in the parity error bit.
1.18
Multidrop (9-bit) Mode - Transmitter
This feature simplifies sending an address byte (9th bit = 1) and improves the efficiency of the transmit data
routine for transmitting 9-bit data. In previous generation UARTs, the only way to send an address byte is by
changing the parity to Forced 1 parity, load the address byte in the THR, wait for the byte to be transmitted,
change the parity back to Forced 0 parity, then load data into the TX FIFO. In the XR20M1280, there’s no
waiting required and no changing parity. The transmit routine can set SFR[7]=1, then write the address byte
into the TX FIFO followed immediately by the data bytes. SFR[7] is self-clearing, therefore, if multiple address
bytes need to be transmitted, then SFR[7] will need to be set prior to each address byte written into the TX
FIFO. During initialization, the parity must be set to Force Parity 0 (LCR[5:3] = ’111’).
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