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參數(shù)資料
| 型號： | XR19L220IL40-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 15/43頁 |
| 文件大小： | 0K |
| 描述： | IC UART/TXRX RS232 40QFN |
| 標準包裝： | 490 |
| 特點： | * |
| 通道數(shù)： | 1，UART |
| FIFO's： | 16 字節(jié) |
| 規(guī)程： | RS232 |
| 電源電壓： | 3 V ~ 5.5 V |
| 帶自動流量控制功能： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 40-QFN 裸露焊盤（6x6） |
| 包裝： | 托盤 |
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XR19L220
22
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.2
IER[7]: CTS Input Interrupt Enable (requires EFR bit-4=1)
Logic 0 = Disable the CTS interrupt (default).
Logic 1 = Enable the CTS interrupt. The UART issues an interrupt when CTS pin makes a transition from low
to high.
4.5
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 7, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.5.1
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS is when the CTS pin is de-asserted during auto CTS flow control enabled by EFR bit-7.
RTS is when the RTS pin is de-asserted during auto RTS flow control enabled by EFR bit-6.
Wake-up Interrupt is when the device wakes up from sleep mode. See Sleep Mode section for more details.
4.5.2
Interrupt Clearing:
LSR interrupt is cleared by reading the LSR register (but FIFO error bit does not clear until the character(s)
that generated the interrupt(s) is (are) read from the FIFO).
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading the RHR register.
TXRDY interrupt is cleared by reading the ISR register or writing to the THR register.
MSR interrupt is cleared by reading the MSR register.
Xoff interrupt is cleared by reading the ISR or when Xon character(s) is received.
Special character interrupt is cleared by reading the ISR or after the next character is received.
RTS and CTS flow control interrupts are cleared by reading the MSR register.
Wake-up interrupt is cleared by reading the ISR register.
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