參數(shù)資料
型號(hào)： XR19L210IL40-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 24/43頁(yè)
文件大小： 0K
描述： IC UART/TXRX RS232 40QFN
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
規(guī)程： RS232
電源電壓： 3 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-QFN 裸露焊盤（6x6）
包裝： 托盤
XR19L210
30
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.2
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, MCR bits 2, 5, 6 and 7
to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values.
This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it
is recommended to leave it enabled, logic 1.
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 2, 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 2, 5-7 are set to a logic 0 to be compatible with ST16C550 mode (default).
Logic 1 = Enables the above-mentioned register bits to be modified by the user.
EFR[5]: Special Character Detect Enable
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5.
EFR[6]: Auto RTS Flow Control Enable
RTS output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected,
an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS de-
asserts (HIGH) at one trigger level above the programmed trigger level. RTS will be re-asserted LOW when
FIFO data falls below one trigger level below the programmed trigger level. The RTS output must be asserted
(logic 0) before the auto RTS can take effect. RTS pin will function as a general purpose output when hardware
flow control is disabled.
Logic 0 = Automatic RTS flow control is disabled (default).
Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled (default).
Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS input de-asserts HIGH.
Data transmission resumes when CTS is asserted LOW.
4.16
Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Write Only
These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2.
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