參數(shù)資料
型號(hào)： XR19L210IL40-F
廠商： Exar Corporation
文件頁數(shù)： 21/43頁
文件大小： 0K
描述： IC UART/TXRX RS232 40QFN
標(biāo)準(zhǔn)包裝： 490
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
規(guī)程： RS232
電源電壓： 3 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 40-QFN 裸露焊盤（6x6）
包裝： 托盤
XR19L210
28
SINGLE CHANNEL INTEGRATED UART AND RS-232 TRANSCEIVER
REV. 1.0.2
LSR[7]: Receive FIFO Data Error Flag
Logic 0 = No FIFO error (default).
Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
4.10
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface input signals. In the normal mode of operation,
only the CTS input pin will change. However, all of the modem inputs can be controlled in internal loopback
mode. Lower four bits of this register are used to indicate the changed information. These bits are set to a
logic 1 whenever a signal from the modem changes state. T
MSR[0]: Delta CTS Input Flag
Logic 0 = No change on CTS input (default).
Logic 1 = The CTS input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR Input Flag
Logic 0 = No change on DSR input (default).
Logic 1 = The DSR input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI Input Flag
Logic 0 = No change on RI input (default).
Logic 1 = The RI input has changed from LOW to HIGH, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD Input Flag
Logic 0 = No change on CD input (default).
Logic 1 = Indicates that the CD input has changed state since the last time it was monitored. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
CTS pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto CTS
(EFR bit-7). Auto CTS flow control allows starting and stopping of local data transmissions based on the
modem CTS signal. A HIGH on the CTS pin will stop UART transmitter as soon as the current character has
finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the complement of
the CTS input. However in the loopback mode, this bit is equivalent to the RTS bit in the MCR register. The
CTS input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the complement of the DSR input. In the loopback mode, this bit is equivalent to the DTR bit
in the MCR register. The DSR input may be used as a general purpose input when the modem interface is not
used.
MSR[6]: RI Input Status
Normally this bit is the complement of the RI input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the complement of the CD input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD input may be used as a general purpose input when the modem interface is not used.
4.11
Scratchpad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
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