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參數(shù)資料
| 型號(hào)： | XR17L152CM |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3.3V PCI BUS DUAL UART |
| 中文描述： | 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 42/55頁 |
| 文件大?。?/td> | 318K |
| 代理商： | XR17L152CM |
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DISCONTINUED
XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
42
FCTR[7:6]: TX and RX FIFO Trigger Table Select
These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is
selected the auto RTS flow control trigger level is set to "next FIFO trigger level" for compatibility to ST16C550
and ST16C650 series. RTS/DTR# triggers on the next level of the RX FIFO trigger level, in another word, one
FIFO level above and one FIFO level below. See
Table 13
for complete selection with FCR bit 4-5 and FCTR bit
6-7, i.e. if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes, RTS/DTR# output will de-
asserts at 60 and re-asserts at 16.
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
Table 17
). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Combinations of software flow control can be selected by programming these bits (see
Table 17
).
T
ABLE
17: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
EFR
BIT
-3
C
ONT
-3
EFR
BIT
-2
C
ONT
-2
EFR
BIT
-1
C
ONT
-1
EFR
BIT
-0
C
ONT
-0
T
RANSMIT
AND
R
ECEIVE
S
OFTWARE
F
LOW
C
ONTROL
0
0
0
0
No TX and RX flow control (default and reset)
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1/Xoff1
0
1
X
X
Transmit Xon2/Xoff2
1
1
X
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1/Xoff1
X
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
1
Transmit Xon1/ Xoff1,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0
1
1
1
Transmit Xon2/Xoff2,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
1
1
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0
0
1
1
No transmit flow control,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
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