參數(shù)資料
型號: XR17L152CM
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: 3.3V PCI BUS DUAL UART
中文描述: 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1 MM HEIGHT, TQFP-100
文件頁數(shù): 19/55頁
文件大?。?/td> 318K
代理商: XR17L152CM
XR17L152
3.3V PCI BUS DUAL UART
REV. 1.1.0
á
DISCONTINUED
19
3.1
FIFO
DATA LOADING AND UNLOADING THROUGH THE DEVICE CONFIGURATION REGISTERS
IN 32-BIT FORMAT
The transmit and receive data registers are defined for channels 0 and 1 with each channel having its own
address as shown in
Table 2
for faster loading and unloading. The following paragraphs illustrate the receive
and transmit data registers in more detail.
Each Channel Normal Receive Data FIFO
Address for channels 0 and 1 are at 0x0100 and 0x0300.
Each Channel Normal Transmit Data
FIFO Address for Channel 0 and 1 are at 0x0100 and 0x0300.
R
EAD
RX FIFO,
WITH N
O
E
RRORS
B
YTE
3
B
YTE
2
B
YTE
1
B
YTE
0
Read n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Read n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
W
RITE
TX FIFO
B
YTE
3
B
YTE
2
B
YTE
1
B
YTE
0
Write n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Write n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
PCI Bus
Data Bit-31
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
Receive Data Byte n+3
Receive Data Byte n+2
Receive Data Byte n+1
Receive Data Byte n+0
PCI Bus
Data Bit-0
Channel 0 to 1 ReceiveData in 32-bit alignment through the Configuration Register Address
0x0100 and 0x0300
PCI Bus
Data Bit-31
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
Transmit Data Byte n+3
Transmit Data Byte n+2
Transmit Data Byte n+1
Transmit Data Byte n+0
PCI Bus
Data Bit-0
Channel 0 to 1 Transmit Data in 32-bit alignment through the Configuration Register Address
0x0100 and 0x0300
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