REV. 1.0.4 2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO AC ELECTRICAL CHARACTERISTICS TA = -40<" />
參數(shù)資料
型號(hào): XR16V564IJ-0A-EVB
廠商: Exar Corporation
文件頁(yè)數(shù): 36/54頁(yè)
文件大小: 0K
描述: EVAL BOARD FOR XR16V564 68PLCC
標(biāo)準(zhǔn)包裝: 1
系列: *
XR16V564/564D
41
REV. 1.0.4
2.25V TO 3.6V QUAD UART WITH 32-BYTE FIFO
AC ELECTRICAL CHARACTERISTICS
TA = -40O TO +85OC, VCC IS 2.25 TO 3.6V, 70 PF LOAD WHERE APPLICABLE
SYMBOL
PARAMETER
LIMITS
2.5V ± 10%
MIN
MAX
LIMITS
3.3V ± 10%
MIN
MAX
UNIT
XTAL1
UART Crystal Frequency
24
MHz
ECLK
External Clock Frequency
50
64
MHz
TECLK
External Clock Time Period
10
7
ns
TAS
Address Setup Time (16 Mode)
0
ns
TAH
Address Hold Time (16 Mode)
0
ns
TCS
Chip Select Width (16 Mode)
50
40
ns
TRD
IOR# Strobe Width (16 Mode)
50
40
ns
TDY
Read Cycle Delay (16 Mode)
50
40
ns
TRDV
Data Access Time (16 Mode)
45
35
ns
TDD
Data Disable Time (16 Mode)
10
ns
TWR
IOW# Strobe Width (16 Mode)
50
40
ns
TDY
Write Cycle Delay (16 Mode)
50
40
ns
TDS
Data Setup Time (16 Mode)
15
ns
TDH
Data Hold Time (16 Mode)
5
ns
TADS
Address Setup (68 Mode)
0
ns
TADH
Address Hold (68 Mode)
0
ns
TRWS
R/W# Setup to CS# (68 Mode)
0
ns
TRDA
Data Access Time (68 mode)
45
35
ns
TRDH
Data Disable Time (68 mode)
10
ns
TWDS
Write Data Setup (68 mode)
10
ns
TWDH
Write Data Hold (68 Mode)
5
ns
TRWH
CS# De-asserted to R/W# De-asserted (68 Mode)
10
5
ns
TCSL
CS# Strobe Width (68 Mode)
50
40
ns
TCSD
CS# Cycle Delay (68 Mode)
50
40
ns
TWDO
Delay From IOW# To Output
50
ns
TMOD
Delay To Set Interrupt From MODEM Input
50
ns
TRSI
Delay To Reset Interrupt From IOR#
50
ns
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