REV. 1.0.2 FIGURE 8. R
參數(shù)資料
型號(hào): XR16V2650IL-F
廠商: Exar Corporation
文件頁(yè)數(shù): 6/47頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO 32B DUAL 32QFN
標(biāo)準(zhǔn)包裝: 490
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 32 字節(jié)
規(guī)程: RS232,RS422
電源電壓: 2.25 V ~ 3.6 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(pán)(5x5)
包裝: 托盤(pán)
XR16V2650
14
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
REV. 1.0.2
FIGURE 8. RECEIVER OPERATION IN NON-FIFO MODE
FIGURE 9. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
R e ce ive D a ta S h ift
Re g iste r (R S R )
Re ce ive
D a ta B yte
an d E rro rs
R H R In te rru p t (IS R b it-2 )
Re ce ive D a ta
H o ld in g R e g iste r
(RHR )
R X FIFO 1
16X or 8X o r 4X C lo ck
( D L D [5:4] )
R e ce ive D a ta C h a ra cte rs
D a ta B it
V a lid a tio n
E rro r
Ta g s in
LS R bits
4:2
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X or 4X Clock
( DLD[5:4] )
Error
T
a
gs
(32-
sets)
E
rro
rT
ag
si
n
LSR
bi
ts
4:
2
Receive Data Characters
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
32 bytes by 11-bit
wide FIFO
FIFO
Trigger=16
Data falls to
8
Data fills to
24
Example
: - RX FIFO trigger level selected at 16 bytes
(See Note Below)
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