REV. 1.0.2 HIGH PERFORMANCE DUART WITH 32-BYTE FIFO FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1) (logic 0 = defau" />
參數(shù)資料
型號(hào)： XR16V2650IL-0B-EB
廠商： Exar Corporation
文件頁(yè)數(shù)： 20/47頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD FOR V2650 32QFN
標(biāo)準(zhǔn)包裝： 1
系列： *
XR16V2650
27
REV. 1.0.2
HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)
(logic 0 = default, TX trigger level = 1)
These 2 bits set the trigger level for the transmit FIFO. The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the
FIFO did not get filled over the trigger level on last re-load. Table 11 below shows the selections. EFR bit-4
must be set to ‘1’ before these bits can be accessed.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 11 shows the complete selections.
4.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
TABLE 11: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR
BIT-7
FCR
BIT-6
FCR
BIT-5
FCR
BIT
-4
RECEIVE
TRIGGER LEVEL
TRANSMIT
TRIGGER
LEVEL
COMPATIBILITY
0
1
0
1
0
1
0
1
0
1
0
1
8 (default)
16
24
28
16 (default)
8
24
30
16C550, 16C2550,
16C2552, 16C554,
16C580 compatible.
BIT-1
BIT-0
WORD LENGTH
0
5 (default)
0
1
6
1
0
7
1
8
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XR16V2650IL32 制造商:EXAR 制造商全稱:EXAR 功能描述:HIGH PERFORMANCE DUART WITH 32-BYTE FIFO
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