REV. 1.0.1 4.12 Enhanced Mode Select Register (EMSR) - Write-onl" />
參數(shù)資料
型號： XR16M681IB25-F
廠商： Exar Corporation
文件頁數(shù)： 30/51頁
文件大?。?/td> 0K
描述： IC UART FIFO 64B 25BGA
標(biāo)準(zhǔn)包裝： 714
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 25-WFBGA
供應(yīng)商設(shè)備封裝： 25-BGA（3x3）
包裝： 托盤
其它名稱： 1016-1458
XR16M681IB25-F-ND
XR16M681
36
1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE
REV. 1.0.1
4.12
Enhanced Mode Select Register (EMSR) - Write-only
This register replaces SPR (during a Write) and is accessible only when FCTR[6] = 1.
EMSR[1:0]: Receive/Transmit FIFO Level Count
When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is
operating in.
TABLE 12: SCRATCHPAD SWAP SELECTION
FCTR[6] EMSR[1] EMSR[0] Scratchpad is
0
X
Scratchpad
1
X
0
RX FIFO Level Counter Mode
1
0
1
TX FIFO Level Counter Mode
1
Alternate RX/TX FIFO Counter Mode
During Alternate RX/TX FIFO Level Counter Mode, the first value read after EMSR bits 1-0 have been
asserted will always be the RX FIFO Level Counter. The second value read will correspond with the TX FIFO
Level Counter. The next value will be the RX FIFO Level Counter again, then the TX FIFO Level Counter and
so on and so forth.
EMSR[2]: Send TX Immediately
Logic 0 = Do not send TX immediately (default).
Logic 1 = Send TX immediately. When FIFO is enabled and this bit is set, the next data will be written to the
TX shift register. Thus, the data will be sent out immediately instead of queuing in the FIFO. Every time, only
1 byte will be send out. Once this byte has been sent out, the EMSR[2] will go back to 0 automatically. If
more than 1 byte will be sent out, EMSR[2] needs to be set to 1 for each byte.
EMSR[3]: Invert RTS in RS485 mode
Logic 0 = RTS# output is a logic 0 during TX and a logic 1 during RX (default).
Logic 1 = RTS# output is a logic 1 during TX and a logic 0 during RX.
EMSR[5:4]: Reserved
EMSR[6]: LSR Interrupt Mode
Logic 0 = LSR Interrupt Delayed (default). LSR bits 2, 3, and 4 will generate an interrupt when the character
with the error is in the RHR.
Logic 1 = LSR Interrupt Immediate. LSR bits 2, 3, and 4 will generate an interrupt as soon as the character is
received into the FIFO.
EMSR[7]: Xoff/Special character Interrupt Mode Select
This bit selects how the Xoff and Special character interrupt is cleared. The XON interrupt can only be cleared
by reading the ISR register.
Logic 0 = Xoff interrupt is cleared by either reading ISR register or when an XON character is received.
Special character interrupt is cleared by either reading ISR register or when next character is received.
(default).
Logic 1 = Xoff/Special character interrupt can only be cleared by reading the ISR register.
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