REV. 1.0.1 2.18 Internal Loopback The M681 UART provides an " />
參數(shù)資料
型號(hào): XR16M681IB25-F
廠商: Exar Corporation
文件頁(yè)數(shù): 15/51頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO 64B 25BGA
標(biāo)準(zhǔn)包裝: 714
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS422,RS485
電源電壓: 1.62 V ~ 3.63 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 25-WFBGA
供應(yīng)商設(shè)備封裝: 25-BGA(3x3)
包裝: 托盤
其它名稱: 1016-1458
XR16M681IB25-F-ND
XR16M681
22
1.62V TO 3.63V UART WITH 32-BYTE FIFO AND VLIO INTERFACE
REV. 1.0.1
2.18
Internal Loopback
The M681 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 14 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held HIGH or mark condition while RTS# and DTR# are de-asserted, and CTS#,
DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held HIGH during loopback test else
upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 14. INTERNAL LOOPBACK
TX
RX
M
ode
m
/
G
ene
ra
lP
u
rpose
Control
L
ogi
c
Inte
rnal
D
a
ta
Bus
Line
sand
Control
S
ignals
RT S #
M C R bit-4=1
VC C
T ra n sm it S h ift R e g is te r
(TH R /FIFO )
R ec e iv e S h ift R e gis ter
(RHR/F IF O )
CT S #
DT R#
DS R#
RI#
CD#
OP 1 #
RT S #
CT S #
DT R#
DS R#
RI#
CD #
VC C
OP 2 #
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