XR16M570
15
REV. 1.0.1
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
FIGURE 10. RECEIVER OPERATION IN NON-FIFO MODE
FIGURE 11. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
Receive
Data Byte
and Errors
RHR Interrupt (ISR bit-2)
Receive Data
Holding Register
(RHR)
RXFIFO1
16X or 8X or 4X Clock
( DLD[5:4] )
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
Receive Data S hift
R egister (R S R )
RX FIFO 1
16X or 8X or 4X C lock
( DLD[5:4] )
Err
o
rT
a
g
s
(16
-se
ts
)
Er
ro
rT
a
g
s
i
n
LS
R
b
it
s
4:
2
R eceive D ata C haracters
D ata B it
V alidation
Receive
D ata FIF O
Receive
Data
Receive Data
B yte and E rrors
R H R Interrupt (IS R bit-2) program m ed for
desired FIFO trigger level.
FIFO is E nabled by F C R bit-0=1
R TS # de-asserts w hen data fills above the flow
control trigger level to suspend rem ote transm itter.
E nable by E FR bit-6=1, M C R bit-1.
R TS# re-asserts w hen data falls below the flow
control trigger level to restart rem ote transm itter.
E nable by E FR bit-6=1, M C R bit-1.
16 bytes by 11-bit w ide
FIFO
T rigger=8
D ata falls to
4
D ata fills to
14
E xam ple
: - R X F IF O trigger level selected at 8 bytes
(See N ote Below )