參數(shù)資料
型號： XR16M570IL32TR-F
廠商： Exar Corporation
文件頁數(shù)： 50/50頁
文件大小： 0K
描述： IC UART FIFO 16B 32QFN
標(biāo)準(zhǔn)包裝： 3,000
特點： *
通道數(shù)： 1，UART
FIFO's： 16 字節(jié)
規(guī)程： RS232，RS422，RS485
電源電壓： 1.62 V ~ 3.63 V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
XR16M570
9
REV. 1.0.1
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 16-BYTE FIFO
2.3
Device Reset
The RESET input resets the internal registers and the serial interface outputs to their default state (see
Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset function in
the device. Following a power-on reset or an external reset, the M570 is software compatible with previous
generation of UARTs, XR16L570 and ST16C550.
2.4
Internal Registers
The M570 has a set of 16550 compatible registers for controlling, monitoring and data loading and unloading.
These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER),
a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control
registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM/DLD), and a user accessible
scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the M570 offers enhanced feature registers (EFR, Xon1/
Xoff 1, Xon2/Xoff 2, DLD, FCTR, EMSR and FC) that provide automatic RTS and CTS hardware flow control,
automatic Xon/Xoff software flow control, 9-bit (Multidrop) mode, auto RS-485 half duplex control, different
baud rate for TX and RX and fractional baud rate generator. All the register functions are discussed in full
detail later in “Section 3.0, UART INTERNAL REGISTERS” on page 23.
2.5
INT Ouput
The interrupt outputs change according to the operating mode and enhanced features setup. Table 1 and 2
summarize the operating behavior for the transmitter and receiver. Also see Figure 19 through 22.
TABLE 1: INT PIN OPERATION FOR TRANSMITTER
FCR BIT-0 = 0 (FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin
LOW = One byte in THR
HIGH = THR empty
LOW = FIFO above trigger level
HIGH = FIFO below trigger level or FIFO empty
TABLE 2: INT PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0 (FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin
HIGH = One byte in RHR
LOW = RHR empty
LOW = FIFO below trigger level
HIGH = FIFO above trigger level or RX Data Timeout
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