XR16M2750
12
1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.0.0
FIGURE 5. BAUD RATE GENERATOR
TABLE 5: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required
Output Data
Rate
DIVISOR FOR
16x Clock
(Decimal)
DIVISOR
OBTAINABLE IN
M2750
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
DLD PROGRAM
VALUE (HEX)
DATA ERROR
RATE (%)
400
3750
E
A6
0
2400
625
2
71
0
4800
312.5
312 8/16
1
38
8
0
9600
156.25
156 4/16
0
9C
4
0
10000
150
0
96
0
19200
78.125
78 2/16
0
4E
2
0
25000
60
0
3C
0
28800
52.0833
52 1/16
0
34
1
0.04
38400
39.0625
39 1/16
0
27
1
0
50000
30
0
1E
0
57600
26.0417
26 1/16
0
1A
1
0.08
75000
20
0
14
0
100000
15
0
F
0
115200
13.0208
13
0
D
0
0.16
153600
9.7656
9 12/16
0
9
C
0.16
200000
7.5
7 8/16
0
7
8
0
225000
6.6667
6 11/16
0
6
B
0.31
230400
6.5104
6 8/16
0
6
8
0.16
250000
6
0
6
0
300000
5
0
5
0
400000
3.75
3 12/16
0
3
C
0
460800
3.2552
3 4/16
0
3
4
0.16
500000
3
0
3
0
750000
2
0
2
0
921600
1.6276
1 10/16
0
1
A
0.16
1000000
1.5
1 8/16
0
1
8
0
XTAL1
XTAL2
Crystal
Osc/
Buffer
MCR Bit-7=0
(default)
MCR Bit-7=1
DLL, DLM and DLD
Registers
Prescaler
Divide by 1
Prescaler
Divide by 4
16X or 8X
Sampling
Rate Clock
to Transmitter
and Receiver
To Other
Channel
Fractional Baud
Rate Generator
Logic