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參數(shù)資料
| 型號(hào)： | XR16L2750IMTR-F |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 5/48頁(yè) |
| 文件大小： | 0K |
| 描述： | IC UART FIFO 64B DUAL 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 特點(diǎn)： | * |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 64 字節(jié) |
| 規(guī)程： | RS232，RS485 |
| 電源電壓： | 2.25 V ~ 5.5 V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
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xr
XR16L2750
REV. 1.2.1
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
13
2.12.1
Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
NOTE: Table-B selected as Trigger Table for
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Data S hift
Register (R S R )
Receive
D ata B yte
and E rrors
RHR Interrupt (IS R bit-2)
Receive Data
H olding R egister
(RHR)
RXF IF O 1
16X or 8X C lock
(EM S R bit-7)
Receive Data Characters
D ata Bit
V alidation
Error
T ags in
LS R bits
4:2
Receive Data Shift
Register (RSR)
RXFIFO1
16X or 8X Clock
(EMSR bit-7)
Er
ro
rT
ag
s
(6
4-set
s)
E
rro
rT
ag
s
in
LSR
bits
4:2
64 bytes by 11-bit
wide
FIFO
Receive Data Characters
FIFO
Trigger=16
Example
:
- RX FIFO trigger level selected at 16
bytes
(See Note Below)
Data fills to
24
Data falls to
8
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-1.
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相關(guān)代理商/技術(shù)參數(shù) |
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| XR16L2751 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE |
| XR16L2751_05 | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE |
| XR16L2751CM | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.25V TO 5.5V DUART WITH 64-BYTE FIFO AND POWERSAVE |
| XR16L2751CM-0A-EB | 功能描述:UART 接口集成電路 Supports L2751 48 ld TQFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16L2751CM-0B-EB | 功能描述:UART 接口集成電路 Supports L2751 48 ld TQFP, PCI Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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