參數資料
型號: XR16L2552IJTR-F
廠商: Exar Corporation
文件頁數: 13/45頁
文件大小: 0K
描述: IC UART FIFO 16B DUAL 44PLCC
標準包裝: 500
特點: *
通道數: 2,DUART
FIFO's: 16 字節(jié)
規(guī)程: RS232
電源電壓: 2.25 V ~ 5.5 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應商設備封裝: 44-PLCC(16.59x16.59)
包裝: 帶卷 (TR)
XR16L2552
20
2.25V TO 5.5V DUART WITH 16-BYTE FIFO
REV. 1.1.2
2.20
Internal Loopback
The L2552 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal. Also, Auto RTS/
CTS is not supported during internal loopback.
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
TXA/TXB
RXA/RXB
Mode
m
/
G
eneral
Purpose
Control
Logic
Inter
n
al
D
a
ta
Bus
Lines
and
C
o
ntrol
Signals
RTSA#/RTSB#
MCR bit-4=1
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB#
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
(OP2A#/OP2B#)
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