參數(shù)資料
型號: XR16C854CQ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO
中文描述: 4 CHANNEL(S), 2M bps, SERIAL COMM CONTROLLER, PQFP100
封裝: 14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù): 35/51頁
文件大?。?/td> 476K
代理商: XR16C854CQ
XR16C854
35
Rev. 1.00P
FCTR BIT-7:
Programmable trigger register select.
0 = Receiver programmable trigger level register is
selected.
1 = Transmitter programmable trigger level register is
selected.
TRIGGER LEVEL / FIFO DATA COUNT REGISTER
User programmable transmit / receive trigger level
register.
TRG BIT 0-7: Write only.
these bits are used to programmed desire trigger
levels that are not available in standard tables.
TRG BIT 0-7: Read only.
Transmit / receive FIFO count. Number of characters
in transmit or receive FIFO can be read via this
register.
ENHANCED MODE SELECT REGISTER
This register is accessible only when FCTR Bit-6 is set
to 1.
EMSR BIT-0: Write only
0 = Receive FIFO count register. The scratch pad
register is used to provide the receive FIFO count
when it is read.
1 = Transmit FIFO count register. The scratch pad
register is used to provide the transmit FIFO count
when it is read.
EMSR BIT-1: Write only
0 = Normal.
1 = Alternate receive - transmit FIFO count. When
EMSR Bit-0=1 and EMSR Bit=1, scratch pad register
is used to provide the receive - transmit FIFO count
when it is read every alternate read cycle. The TRG
Bit-7 will provide the FIFO count mode information,
TRG Bit-7=0 receive mode, TRG Bit-7=1 transmit
mode.
EMSR BIT 4-7:
Reserved for future use.
XR16C854 EXTERNAL RESET CONDITIONS
REGISTERS
RESET STATE
IER
ISR
LCR
MCR
LSR
IER BITS 0-7=0
ISR BIT-0=1, ISR BITS 1-7=0
LCR BITS 0-7=0
MCR BITS 0-7=0
LSR BITS 0-4=0,
LSR BITS 5-6=1 LSR, BIT 7=0
MSR BITS 0-3=0,
MSR BITS 4-7= input signals
FCR BITS 0-7=0
EFR BITS 0-7=0
FCTR BITS 0-7=0
EMSR BITS 0-7=0
TRG BITS 0-7=0
MSR
FCR
EFR
FCTR
EMSR
TRG
SIGNALS
RESET STATE
TX A-D
-RTS A-D
-DTR A-D
-RXRDY A-D
-TXRDY A-D
High
High
High
High
Low
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