參數(shù)資料
型號: XR16C854CQ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO
中文描述: 4 CHANNEL(S), 2M bps, SERIAL COMM CONTROLLER, PQFP100
封裝: 14 X 20 MM, PLASTIC, QFP-100
文件頁數(shù): 16/51頁
文件大?。?/td> 476K
代理商: XR16C854CQ
XR16C854
16
Rev. 1.00P
FIFO Operation
The 128 byte transmit and receive data FIFOs are
enabled by the FIFO Control Register (FCR) bit-0.
With 16C554 devices, the user can set the receive
trigger level but not the transmit trigger level. The 854
provides independent trigger levels for both receiver
and transmitter. To remain compatible with
ST16C554, the transmit interrupt trigger level is set to
8 following a reset. It should be noted that the user can
set the transmit trigger levels by writing to the FCR
register, but activation will not take place until EFR bit-
4 is set to a logic 1. The receiver FIFO section includes
a time-out function to ensure data is delivered to the
external CPU. An interrupt is generated whenever the
Receive Holding Register (RHR) has not been read
following the loading of a character or the receive
trigger level has not been reached. (see hardware flow
control for a description of this timing).
Hardware Flow Control
When automatic hardware flow control is enabled, the
854 monitors the -CTS pin for a remote buffer overflow
indication and controls the -RTS pin for local buffer
overflows. Automatic hardware flow control is se-
lected by setting bits 6 (RTS) and 7 (CTS) of the EFR
register to a logic 1. If -CTS transitions from a logic 0
to a logic 1 indicating a flow control request, ISR bit-
5 will be set to a logic 1 (if enabled via IER bit 6-7), and
the 854 will suspend TX transmissions as soon as the
stop bit of the character in process is shifted out.
Transmission is resumed after the -CTS input returns
to a logic 0, indicating more data may be sent.
With the Auto RTS function enabled, an interrupt is
generated when the receive FIFO reaches the pro-
grammed trigger level. The -RTS pin will not be forced
to a logic 1 (RTS Off), until the receive FIFO reaches
the next trigger level
.
However, the -RTS pin will
return to a logic 0 after the data buffer (FIFO) is
unloaded to the next trigger level below the pro-
grammed trigger. However, under the above de-
scribed conditions the 854 will continue to accept data
until the receive FIFO is full.
Selected
Trigger
Level
(characters)
INT
Pin
-RTS
Logic 1
(characters)
-RTS
Logic 0
(characters)
Activation
8
16
56
60
8
16
56
60
16
56
60
60
0
8
16
56
相關(guān)PDF資料
PDF描述
XR16C854CV QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO
XR16C854DCV QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO
XR16C854DIV QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO
XR16C854IJ QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO
XR16C854IQ QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO
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XR16C854CQ-0A-EVB 功能描述:UART 接口集成電路 Supports C854 100 ld QFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16C854CQ-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16C854CQTR-F 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
XR16C854CV 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO
XR16C854CV-0A-EVB 功能描述:UART 接口集成電路 Supports C854 64 ld TQFP, ISA Interface RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel