REV. 2.3.1 34 LCR[7]: Baud Rate Divisors Enable Baud rate generator divisor (DLL/DLM) enable." />
參數(shù)資料
型號(hào)： XR16C850IJ-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 28/56頁(yè)
文件大?。?/td> 0K
描述： IC UART FIFO 128B 44PLCC
標(biāo)準(zhǔn)包裝： 27
特點(diǎn)： *
通道數(shù)： 1，UART
FIFO's： 128 字節(jié)
規(guī)程： RS485
電源電壓： 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 管件
其它名稱： 1016-1568-5
1016-1568-5-ND
1016-1657
XR16C850IJ-F-ND
XR16C850
xr
2.97V TO 5.5V UART WITH 128-BYTE FIFO
REV. 2.3.1
34
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
Logic 0 = Data registers are selected (default).
Logic 1 = Divisor latch registers are selected.
4.7
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
Logic 0 = Force DTR# output to a logic 1 (default).
Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output
The RTS# pin is a modem control output and may be used for automatic hardware flow control by enabled by
EFR bit-6. If the modem interface is not used, this output may be used as a general purpose output.
Logic 0 = Force RTS# output to a logic 1 (default).
Logic 1 = Force RTS# output to a logic 0.
MCR[2]: OP1# Output/Auto RS485 Control
OP1# is a general purpose output. If Auto RS-485 mode is enabled, this works as the half-duplex direction
control output. See FCTR[3] for more details.
Logic 0 = OP1# output is at logic 1.
Logic 1 = OP1# output is at logic 0.
MCR[3]: OP2# or IRQn Enable during PC Mode
OP2# is a general purpose output available during the Intel bus interface mode of operation. In the PC bus
mode, this bit enables the IRQn operation. See PC Mode section and IRQn pin description. The OP2# output
is not available in the PC Mode.
During Intel Bus Mode Operation:
Logic 0 = Sets OP2# output to a logic 1 (default).
Logic 1 = Sets OP2# output to a logic 0.
During PC Mode Operation:
See Table 3 for more details.
MCR[4]: Internal Loopback Enable
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and Figure 16.
MCR[5]: Xon-Any Enable
Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and
the 850 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
Logic 0 = Enable the standard modem receive and transmit input/output interface (default).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX output will be a logic 0 during idle data conditions.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XR16C850IJTR-F 制造商:Exar Corporation 功能描述:UART 1-CH 128Byte FIFO 3.3V/5V 44-Pin PLCC T/R
XR16C850IM 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述:
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XR16C850IP 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART|CMOS|DIP|40PIN|PLASTIC
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