REV. 2.3.1 2.97V TO 5.5V UART WITH 128-BYTE FIFO 25 3.0 UART INTERNAL REGISTERS The 850 has a set of configuration registers select" />
參數(shù)資料
型號(hào): XR16C850IJ-F
廠商: Exar Corporation
文件頁(yè)數(shù): 18/56頁(yè)
文件大?。?/td> 0K
描述: IC UART FIFO 128B 44PLCC
標(biāo)準(zhǔn)包裝: 27
特點(diǎn): *
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.97 V ~ 5.5 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱(chēng): 1016-1568-5
1016-1568-5-ND
1016-1657
XR16C850IJ-F-ND
xr
XR16C850
REV. 2.3.1
2.97V TO 5.5V UART WITH 128-BYTE FIFO
25
3.0 UART INTERNAL REGISTERS
The 850 has a set of configuration registers selected by address lines A0, A1 and A2. The 16C550 compatible
registers can be accessed when LCR[7] = 0 and the baud rate generator divisor registers can be accessed
when LCR[7] = 1 and LCR
≠ 0xBF. The enhanced registers are accessible only when LCR = 0xBF. The
complete register set is shown on Table 7 and Table 8.
TABLE 7: XR16C850 UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES
REGISTER
READ/WRITE
COMMENTS
16C550 COMPATIBLE REGISTERS
0 0 0
RHR - Receive Holding Register
THR - Transmit Holding Register
Read-only
Write-only
LCR[7] = 0
0 0 0
DLL - Div Latch Low Byte
Read/Write
LCR[7] = 1, LCR
≠ 0xBF
0 0 1
DLM - Div Latch High Byte
Read/Write
0 0 0
DREV - Device Revision Code
Read-only
DLL, DLM = 0x00,
LCR[7] = 1, LCR
≠ 0xBF
0 0 1
DVID - Device Identification Code
Read-only
0 0 1
IER - Interrupt Enable Register
Read/Write
LCR[7] = 0
0 1 0
ISR - Interrupt Status Register
FCR - FIFO Control Register
Read-only
Write-only
0 1 1
LCR - Line Control Register
Read/Write
1 0 0
MCR - Modem Control Register
Read/Write
LCR[7] = 0
1 0 1
LSR - Line Status Register
Reserved
Read-only
Write-only
1 1 0
MSR - Modem Status Register
Reserved
Read-only
Write-only
1 1 1
SPR - Scratch Pad Register
Read/Write
LCR[7] = 0, FCTR[6] = 0
1 1 1
FLVL - TX/RX FIFO Level Counter Register
Read-only
LCR[7] = 0, FCTR[6] = 1
1 1 1
EMSR - Enhanced Mode Select Register
Write-only
ENHANCED REGISTERS
0 0 0
TRG - TX/RX FIFO Trigger Level Reg
FC - TX/RX FIFO Level Counter Register
Write-only
Read-only
LCR = 0xBF
0 0 1
FCTR - Feature Control Reg
Read/Write
0 1 0
EFR - Enhanced Function Reg
Read/Write
1 0 0
Xon-1 - Xon Character 1
Read/Write
1 0 1
Xon-2 - Xon Character 2
Read/Write
1 1 0
Xoff-1 - Xoff Character 1
Read/Write
1 1 1
Xoff-2 - Xoff Character 2
Read/Write
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