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參數(shù)資料
| 型號： | XR16C850CP |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control |
| 中文描述： | 1 CHANNEL(S), 2.25M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 8/55頁 |
| 文件大小： | 331K |
| 代理商： | XR16C850CP |
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XR16C850
8
Rev. 1.20
MCR bit-3 is set to a logic 1, interrupts are enabled
in the interrupt enable register (IER), and when an
interrupt condition exists. Interrupt conditions in-
clude: receiver errors, available receiver buffer data,
transmit buffer empty, or when a modem status flag
is detected. During STD mode operation the three
state mode is disabled and this pin functions as INT
(Interrupt Request).
IRQB/-RXRDY
29
32
29
32
O
Interrupt Request “B” or Receive Ready (three state,
dual function) -. During PC mode operation, a logic
1 indicates an interrupt IRQB (see further descrip-
tion under the IRQA). During the STD mode a logic
0 indicates receive data ready status, i.e. the RHR
is full or the FIFO has one or more RX characters
available for unloading. This pin goes to a logic 0
when the FIFO/RHR is full or when there are more
characters available in either the FIFO or RHR.
IRQC/-TXRDY
24
27
23
25
O
Interrupt Request “C” or Transmit Ready (three
state, dual function) - During PC mode operation, a
logic 1 on this pin indicates an interrupt IRQC (see
further description under the IRQA). During the STD
mode buffer ready status is indicated by a logic 0,
i.e., at least one location is empty and available in
the FIFO or THR. This pin goes to a logic 1 when
there are no more empty locations in the FIFO or
THR.
-LPT-1 /
-BAUDOUT
15
17
12
12
O
Baud Rate Generator Output or Line Printer Port-1
Decode Logic Output. (dual function, active low) -
When the PC mode is selected, the baud rate
generator clock output is internally connected to the
RCLK input. This pin then functions as the LPT-1
printer port decode logic output, see table 2. During
STD mode operation, this pin provides the 16X clock
of the selected data rate from the baud rate genera-
tor. The RCLK pin must be connected externally to
-BAUDOUT when the receiver is operating at the
same data rate.
-LPT2/-DDIS
23
26
22
24
O
Drive Disable or Line Printer Port-2 Decode Logic
Output (dual function, active low) - When the PC
Symbol
Pin
Signal
type
Pin Description
40
44
48
52
SYMBOL DESCRIPTION
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XR16C850CQ | 制造商:EXAR 制造商全稱:EXAR 功能描述:UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control |
| XR16C850IJ | 制造商:EXAR 制造商全稱:EXAR 功能描述:2.97V TO 5.5V UART WITH 128-BYTE FIFO |
| XR16C850IJ-F | 功能描述:UART 接口集成電路 UARTW/128BYTE FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C850IJTR-F | 制造商:Exar Corporation 功能描述:UART 1-CH 128Byte FIFO 3.3V/5V 44-Pin PLCC T/R |
| XR16C850IM | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
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