參數(shù)資料
型號(hào): XR16C850CJ
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control
中文描述: 1 CHANNEL(S), 2.25M bps, SERIAL COMM CONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁(yè)數(shù): 31/55頁(yè)
文件大?。?/td> 331K
代理商: XR16C850CJ
XR16C850
31
Rev. 1.20
LCR BIT-3:
Parity or no parity can be selected via this bit.
Logic 0 = No parity (normal default condition)
Logic 1 = A parity bit is generated during the transmis-
sion, the receiver checks and reports parity error in the
LSR register. The parity is not presented in the received
data byte.
LCR BIT-4:
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted data. The receiver
must be programmed to check the same format. (nor-
mal default condition)
Logic 1 = EVEN Parity
is generated by forcing an even
number of logic 1’s in the transmitted data. The receiver
must be programmed to check the same format.
LCR BIT-5:
If the parity bit is enabled, LCR BIT-5 selects the forced
parity format.
LCR BIT-5 = logic 0, parity is not forced (normal default
condition)
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit
is forced to a logical 1 for the transmit and receive data.
LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit
is forced to a logical 0 for the transmit and receive data.
LCR
Bit-3
LCR
Bit-4
LCR
Bit-5
Parity selection
0
1
1
1
1
X
0
1
0
1
X
0
0
1
1
No parity
Odd parity
Even parity
Force parity “1”
Forced parity “0”
LCR BIT-6:
When enabled the Break control bit causes a break
condition to be transmitted (the TX output is forced to a
logic 0 state). This condition exists until disabled by
setting LCR bit-6 to a logic 0.
Logic 0 = No TX break condition. (normal default
condition)
Logic 1 = Forces the transmitter output (TX) to a logic
0 for alerting the remote receiver to a line break condi-
tion.
LCR BIT-7:
The internal baud rate counter latch and Enhance
Feature mode enable.
Logic 0 = Divisor latch disabled. (normal default condi-
tion)
Logic 1 = Select baud rate divisors (DLL and DLM) and
enhanced feature register set enabled
Modem Control Register (MCR)
This register controls the interface with the modem or a
peripheral device.
MCR BIT-0:
Logic 0 = Force -DTR output to a logic 1. (normal default
condition)
Logic 1 = Force -DTR output to a logic 0.
MCR BIT-1:
Logic 0 = Force -RTS output to a logic 1. (normal default
condition)
Logic 1 = Force -RTS output to a logic 0.
Automatic RTS may be used for hardware flow control
by enabling EFR bit-6 (See EFR bit-6).
MCR BIT-2:
Logic 0 = Set -OP1 output to a logic 1. (normal default
condition)
Logic 1 = Set -OP1 output to a logic 0.
MCR BIT-3:
Logic 0 = Set -OP2 output to a logic 1 (STD mode).
Forces IRQx outputs to three state mode during the PC
mode. (normal default condition)
Logic 1 = Set -OP2 output to a logic 0 (STD mode).
Forces the IRQx outputs to the active mode during the
PC mode.
MCR BIT-4:
Logic 0 = Disable loop-back mode. (normal default
condition)
Logic 1 = Enable local loop-back mode (diagnostics).
MCR BIT-5:
Logic 0 = Disable Xon Any function (for 16C550 compat-
ibility). (normal default condition)
Logic 1 = Enable Xon Any function. In this mode any RX
character received will enable Xon.
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