參數(shù)資料
型號： XR16C2852CJ
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 3.3V AND 5V DUART WITH 128-BYTE FIFO
中文描述： 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 41/42頁
文件大小： 574K
代理商： XR16C2852CJ
XR16C2852
3.3V AND 5V DUART WITH 128-BYTE FIFO
REV. 2.0.0
á
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
A
PPLICATIONS
.............................................................................................................................................1
F
EATURES
...................................................................................................................................................1
F
IGURE
1. XR16C2852 B
LOCK
D
IAGRAM
................................................................................................................................................ 1
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
............................................................................................................................................................. 2
ORDERING
INFORMATION
..............................................................................................................................2
PIN DESCRIPTIONS .........................................................................................................3
1.0 Product DESCRIPTION ........................................................................................................... 5
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................. 6
2.1 CPU I
NTERFACE
................................................................................................................................. 6
F
IGURE
3. XR16C2852 D
ATA
B
US
I
NTERCONNECTIONS
......................................................................................................................... 6
2.2 D
EVICE
R
ESET
.................................................................................................................................... 6
2.3 D
EVICE
I
DENTIFICATION
AND
R
EVISION
................................................................................................. 6
2.4 C
HANNEL
A
AND
B S
ELECTION
............................................................................................................. 6
2.5 C
HANNEL
A
AND
B I
NTERNAL
R
EGISTERS
............................................................................................. 7
2.6 S
IMULTANEOUS
W
RITE
TO
C
HANNEL
A
AND
B ...................................................................................... 7
T
ABLE
1: C
HANNEL
A
AND
B S
ELECT
....................................................................................................................................................... 7
2.7 DMA M
ODE
........................................................................................................................................ 7
T
ABLE
2: TXRDY#
AND
RXRDY# O
UTPUTS
IN
FIFO
AND
DMA M
ODE
.................................................................................................... 7
2.8 INTA
AND
INTB O
UPUTS
..................................................................................................................... 8
T
ABLE
3: INTA
AND
INTB P
INS
O
PERATION
FOR
T
RANSMITTER
................................................................................................................ 8
T
ABLE
4: INTA
AND
INTB P
IN
O
PERATION
F
OR
R
ECEIVER
....................................................................................................................... 8
2.9 C
RYSTAL
O
SCILLATOR
OR
E
XT
. C
LOCK
I
NPUT
...................................................................................... 8
F
IGURE
4. T
YPICAL
OSCILLATOR
CONNECTIONS
........................................................................................................................................ 8
2.10 P
ROGRAMMABLE
B
AUD
R
ATE
G
ENERATOR
......................................................................................... 8
F
IGURE
5. E
XTERNAL
C
LOCK
C
ONNECTION
FOR
E
XTENDED
D
ATA
R
ATE
................................................................................................... 9
F
IGURE
6. B
AUD
R
ATE
G
ENERATOR
AND
P
RESCALER
............................................................................................................................... 9
T
ABLE
5: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
.............................................................................. 10
2.11 T
RANSMITTER
.................................................................................................................................. 10
2.11.1 Transmit Holding Register (THR) - Write Only....................................................................................... 10
2.11.2 Transmitter Operation in non-FIFO Mode .............................................................................................. 10
F
IGURE
7. T
RANSMITTER
O
PERATION
IN
NON
-FIFO M
ODE
...................................................................................................................... 11
2.11.3 Transmitter Operation in FIFO Mode...................................................................................................... 11
F
IGURE
8. T
RANSMITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
............................................................................................. 11
2.12 R
ECEIVER
....................................................................................................................................... 11
2.12.1 Receive Holding Register (RHR) - Read-Only ....................................................................................... 12
F
IGURE
9. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
........................................................................................................................... 12
F
IGURE
10. R
ECEIVER
O
PERATION
IN
FIFO
AND
A
UTO
RTS F
LOW
C
ONTROL
M
ODE
............................................................................... 12
2.13 A
UTO
RTS (H
ARDWARE
) F
LOW
C
ONTROL
........................................................................................ 13
2.14 A
UTO
RTS H
YSTERESIS
................................................................................................................. 13
2.15 A
UTO
CTS F
LOW
C
ONTROL
............................................................................................................ 13
F
IGURE
11. A
UTO
RTS
AND
CTS F
LOW
C
ONTROL
O
PERATION
.............................................................................................................. 14
2.16 A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
................................................................................ 14
T
ABLE
6: A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
....................................................................................................................... 15
2.17 S
PECIAL
C
HARACTER
D
ETECT
........................................................................................................ 15
2.18 A
UTO
RS485 H
ALF
-
DUPLEX
C
ONTROL
............................................................................................ 15
2.19 I
NFRARED
M
ODE
............................................................................................................................. 15
F
IGURE
12. I
NFRARED
T
RANSMIT
D
ATA
E
NCODING
AND
R
ECEIVE
D
ATA
D
ECODING
................................................................................. 16
2.20 S
LEEP
M
ODE
WITH
A
UTO
W
AKE
-U
P
................................................................................................ 16
2.21 I
NTERNAL
L
OOPBACK
...................................................................................................................... 17
F
IGURE
13. I
NTERNAL
L
OOP
B
ACK
IN
C
HANNEL
A
AND
B........................................................................................................................ 17
3.0 UART INTERNAL REGISTERS ............................................................................................. 18
T
ABLE
7: UART CHANNEL A AND B UART INTERNAL REGISTERS............................................................................................. 18
T
ABLE
8: INTERNAL REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1.............................................. 19
4.0 INTERNAL Register descriptions ........................................................................................ 20
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