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參數資料
| 型號： | XR16C2852CJ |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| 中文描述： | 2 CHANNEL(S), 3.125M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數： | 23/42頁 |
| 文件大?。?/td> | 574K |
| 代理商： | XR16C2852CJ |
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XR16C2852
REV. 2.0.0
3.3V AND 5V DUART WITH 128-BYTE FIFO
á
23
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO
(default).
Logic 1 = Enable the transmit and receive FIFOs.
This bit must be set to logic 1 when other FCR bits
are written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive
FIFO
reset (default)
Logic 1 = Reset the receive FIFO pointers and
FIFO level counter logic (the receive shift register is
not cleared or altered). This bit will return to a logic
0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and
FIFO level counter logic (the transmit shift register
is not cleared or altered). This bit will return to a
logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the -TXRDY and -RXRDY
pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
These 2 bits set the trigger level for the transmit FIFO.
The UART will issue a transmit interrupt when the
number of characters in the FIFO falls below the se-
lected trigger level, or when it gets empty in case that
the FIFO did not get filled over the trigger level on last
re-load. Table 10
below shows the selections. EFR
bit-4 must be set to ‘1’ before these bits can be ac-
cessed. Note that the receiver and the transmitter
cannot use different trigger tables. Whichever selec-
tion is made last applies to both the RX and TX side.
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 5-4 are associated with these 2 bits.
These 2 bits are used to set the trigger level for the
receive FIFO. The UART will issue a receive interrupt
when the number of the characters in the FIFO cross-
es the trigger level. Table 10 shows the complete se-
lections. Note that the receiver and the transmitter
cannot use different trigger tables. Whichever selec-
tion is made last applies to both the RX and TX side.
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| XR16C2852IJ | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
| XR16C850CJ | UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control |
| XR16C850CM | UART with 128-byte FIFO’s FIFO Counters and Half-duplex Control |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XR16C2852CJ-0A-EB | 功能描述:UART 接口集成電路 Supports C2852 44 ld PLCC, ISA Interface RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2852CJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2852CJTR-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| XR16C2852IJ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| XR16C2852IJ-F | 功能描述:UART 接口集成電路 UART RoHS:否 制造商:Texas Instruments 通道數量:2 數據速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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