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參數(shù)資料
| 型號： | XR-T7295IP |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | DS3/Sonet STS-1 Integrated Line Receiver |
| 中文描述： | RECEIVER, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 226K |
| 代理商： | XR-T7295IP |
XR-T7295
3
Rev. 1.05
PIN CONFIGURATION
V
DD
A
LOSTHR
REQB
ICT
RPDATA
RNDATA
RCLK
EXCLK
V
DD
C
V
DD
D
GNDA
R
IN
TMC1
LPF1
LPF2
TMC2
RLOS
RLOL
GNDD
GNDC
20 Lead PDIP (0.300”)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
A
LOSTHR
REQB
ICT
RPDATA
RNDATA
RCLK
EXCLK
V
DD
C
V
DD
D
GNDA
R
IN
TMC1
LPF1
LPF2
TMC2
RLOS
RLOL
GNDD
GNDC
20 Lead SOJ (Jedec, 0.300”)
20
1
11
10
2
3
4
5
6
7
15
14
13
12
17
16
8
9
19
18
PIN DESCRIPTION
Pin #
1
2
Symbol
GNDA
R
IN
Type
Description
Analog Ground.
Receive Input.
Analog receive input. This pin is internally biased at about 1.5V in series
with 50 k
.
Test Mode Control 1 and 2
. Internal test modes are enabled within the device by using
TMC1 and TMC2. Users must tie these pins to the ground plane.
PLL Filter 1 and 2
. An external capacitor (0.1
μ
F
Receive Loss-of-signal.
This pin us set high on loss of the data signal at the receive input.
(See Table 7)
Receive PLL Loss-of-lock.
This pin is set high on loss of PLL frequency lock.
Digital Ground for PLL Clock
. Ground lead for all circuitry running synchronously with
PLL clock.
Digital Ground for EXCLK
. Ground lead for all circuitry running synchronously with
EXCLK.
5V Digital Supply (
10%) for PLL Clock.
Power for all circuitry running synchronously
with PLL clock.
5V Digital Supply (
10%) for EXCLK
. Power for all circuitry running synchronously with
EXCLK.
External Reference Clock
. A valid DS3 (44.736MHz
100ppm) clock must be provided at this input. The duty cycle of EXCLK, referenced to V
DD
/2 levels, must be within 40% - 60% with a minimum rise and fall time (10% to 90%) of 5ns.
Receive Clock
. Recovered clock signal to the terminal equipment.
Receive Negative Data
. Negative pulse data output to the terminal equipment. (See
Figure 11.)
Receive Positive Data
. Positive pulse data output to the terminal equipment. (See
Figure 11)
In-circuit Test Control (Active-low)
. If ICT is forced low, all digital output pins (RCLK,
RPDATA, RNDATA, RLOS, RLOL) are placed in a high-impedance state to allow for in-cir-
cuit testing. There is an internal pull-up on this pin.
Receive Equalization Bypass
. A high on this pin bypasses the internal equalizer. A low
places the equalizer in the data path.
Loss-of-signal Threshold Control
. The voltage forced on this pin controls the input loss-
of-signal threshold. Three settings are provided by forcing GND, V
DD
/2, or V
DD
. This pin
must be set to the desired level upon power-up and should not be changed during opera-
tion.
5V
Analog Supply
(
10%).
I
3,6
TMC1-TMC2
I
4,5
7
LPF1-LPF2
RLOS
I
20%) is connected between these pins.
O
8
9
RLOL
GNDD
O
10
GNDC
11
V
DD
D
12
V
DD
C
13
EXCLK
I
100ppm) or STS-1 (51.84MHz +
14
15
RCLK
RNDATA
O
O
16
RPDATA
O
17
ICT
I
18
REQB
I
19
LOSTHR
I
20
V
DD
A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR-T7295 | DS3/Sonet STS-1 Integrated Line Receiver |
| XR-T7295IW | DS3/Sonet STS-1 Integrated Line Receiver |
| XR-T7296 | DS3/STS-1, E3 Integrated Line Transmitter |
| XR-T7296IP | DS3/STS-1, E3 Integrated Line Transmitter |
| XR-T7296IW | DS3/STS-1, E3 Integrated Line Transmitter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR-T7295IW | 制造商:EXAR 制造商全稱:EXAR 功能描述:DS3/Sonet STS-1 Integrated Line Receiver |
| XR-T7295SIP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Receiver |
| XR-T7295SIW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ATM/SONET Receiver |
| XR-T7295TIP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Receiver |
| XR-T7295TIW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Receiver |
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