- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376453 > XR-T7295 (Exar Corporation) DS3/Sonet STS-1 Integrated Line Receiver PDF資料下載
參數(shù)資料
| 型號： | XR-T7295 |
| 廠商： | Exar Corporation |
| 英文描述： | DS3/Sonet STS-1 Integrated Line Receiver |
| 中文描述： | DS3/Sonet STS - 1的集成線路接收器 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 226K |
| 代理商： | XR-T7295 |
XR-T7295
7
Rev. 1.05
DS3 SIGNAL REQUIREMENTS AT THE DSX
Pulse characteristics are specified at the DSX-3, which is
an interconnection and test point referred to as the
cross-connect (see Figure 2.) The cross-connect exists
at the point where the transmitted signal reaches the
distribution frame jack. Table 2lists the signal
requirements. Currently, two isolated pulse template
requirements exist: the ACCUNET T45 pulse template
(see Table 3and Figure 4) and the G.703 pulse template
(see Table 4and Figure 5). Table 3and Table 5give the
associated boundary equations for the templates. The
XR-T7295 correctly decodes any transmitted signal that
meets one of these templates at the cross-connect.
Parameter
Specification
Line Rate
44.736 Mbps
20 ppm
Line Code
Bipolar with three-0 substitution (B3ZS)
75
5%
An isolated pulse must fit the template in Figure 4or Figure 5
1
The pulse amplitude may be scaled by
a constant factor to fit the template. The pulse amplitude must be between 0.36vpk and 0.85vpk,
measured at the center of the pulse.
Test Load
Pulse Shape
Power Levels
For and all 1s transmitted pattern, the power at 22.368
the power at 44.736
0.002MHz must be -21.8dBm to -14.3dBm.
2, 3
0.002MHz must be -1.8 to +5.7dBm, and
Notes
1
The pulse template proposed by G.703 standards is shown in Figure 5 and specified in Table 4. The proposed G.703 standards
further state that the voltage n a time slot containing a 0 must not exceed 5% of the peak pulse amplitude, except for the residue
of preceding pulses.
2
The power levels specified by the proposed G.703 standards are identical except that the power is to be measured in 3kHz bands.
3
The all 1s pattern must be a pure all 1s signal, without framing or other control bits.
Table 2. DSX-3 Interconnection Specification
Lower Curve
Upper Curve
Time
Equation
Time
Equation
T
-0.36
0
T
-0.68
0
-0.36
T
+0.28
0.5 1+sin
π
/2
[
1+T/0.18
]
-0.68
T
+0.36
0.5 1+sin
π
/2
[
1+T/0.34
]
0.28
T
0.11e
-3.42(T-0.3)
0.36
T
0.05 + 0.407e
-1.84(T-0.36)
Table 3. DSX-3 Pulse Template Boundaries for ACCUNET T45 Standards (See Figure 4.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR-T7295IW | DS3/Sonet STS-1 Integrated Line Receiver |
| XR-T7296 | DS3/STS-1, E3 Integrated Line Transmitter |
| XR-T7296IP | DS3/STS-1, E3 Integrated Line Transmitter |
| XR-T7296IW | DS3/STS-1, E3 Integrated Line Transmitter |
| XR16C2850 | 3.3V AND 5V DUART WITH 128-BYTE FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR-T7295-1EIP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Receiver |
| XR-T7295-1EIW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM Receiver |
| XRT7295A/96ES -DS3 | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7295A/96ES-DS3 | 功能描述:外圍驅(qū)動器與原件 - PCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT7295A/96ES-E3 | 功能描述:外圍驅(qū)動器與原件 - PCI comeswith XRT7295A RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。